include/configs/r2dplus.h

   1 #ifndef __CONFIG_H
   2 #define __CONFIG_H
   3
   4 #undef DEBUG
   5
   6 #define CONFIG_SH               1
   7 #define CONFIG_SH4              1
   8 #define CONFIG_CPU_SH7751       1
   9 #define CONFIG_CPU_SH_TYPE_R    1
  10 #define CONFIG_R2DPLUS          1
  11 #define __LITTLE_ENDIAN__       1
  12
  13 /*
  14  * Command line configuration.
  15  */
  16 #include <config_cmd_default.h>
  17
  18 #define CONFIG_CMD_DFL
  19 #define CONFIG_CMD_CACHE
  20 #define CONFIG_CMD_FLASH
  21 #define CONFIG_CMD_PCI
  22 #define CONFIG_CMD_NET
  23 #define CONFIG_CMD_PING
  24 #define CONFIG_CMD_IDE
  25 #define CONFIG_CMD_EXT2
  26 #define CONFIG_DOS_PARTITION
  27
  28 /* SCIF */
  29 #define CFG_SCIF_CONSOLE        1
  30 #define CONFIG_BAUDRATE         115200
  31 #define CONFIG_CONS_SCIF1       1
  32 #define BOARD_LATE_INIT         1
  33
  34 #define CONFIG_BOOTDELAY        -1
  35 #define CONFIG_BOOTARGS         "console=ttySC0,115200"
  36 #define CONFIG_ENV_OVERWRITE    1
  37
  38 /* Network setting */
  39 #define CONFIG_NETMASK          255.0.0.0
  40 #define CONFIG_IPADDR           10.0.192.51
  41 #define CONFIG_SERVERIP         10.0.0.1
  42 #define CONFIG_GATEWAYIP        10.0.0.1
  43
  44 /* SDRAM */
  45 #define CFG_SDRAM_BASE          (0x8C000000)
  46 #define CFG_SDRAM_SIZE          (0x04000000)
  47
  48 #define CFG_LONGHELP
  49 #define CFG_PROMPT              "=> "
  50 #define CFG_CBSIZE              256
  51 #define CFG_PBSIZE              256
  52 #define CFG_MAXARGS             16
  53 #define CFG_BARGSIZE            512
  54 /* List of legal baudrate settings for this board */
  55 #define CFG_BAUDRATE_TABLE      { 115200, 57600, 38400, 19200, 9600 }
  56
  57 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE)
  58 #define CFG_MEMTEST_END         (TEXT_BASE - 0x100000)
  59
  60 #define CFG_LOAD_ADDR           (CFG_SDRAM_BASE + 32 * 1024 * 1024)
  61 /* Address of u-boot image in Flash */
  62 #define CFG_MONITOR_BASE        (CFG_FLASH_BASE)
  63 #define CFG_MONITOR_LEN         (128 * 1024)
  64 /* Size of DRAM reserved for malloc() use */
  65 #define CFG_MALLOC_LEN          (256 * 1024)
  66 /* size in bytes reserved for initial data */
  67 #define CFG_GBL_DATA_SIZE       (256)
  68 #define CFG_BOOTMAPSZ           (8 * 1024 * 1024)
  69
  70 /*
  71  * NOR Flash
  72  */
  73 #define CFG_FLASH_CFI
  74 #define CFG_FLASH_CFI_DRIVER
  75
  76 #if defined(CONFIG_R2DPLUS_OLD)
  77 #define CFG_FLASH_BASE          (0xA0000000)
  78 #define CFG_MAX_FLASH_BANKS (1) /* Max number of
  79                                  * Flash memory banks
  80                                  */
  81 #define CFG_MAX_FLASH_SECT  142
  82 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
  83
  84 #else /* CONFIG_R2DPLUS_OLD */
  85
  86 #define CFG_FLASH_BASE          (0xA0000000)
  87 #define CFG_FLASH_CFI_WIDTH     0x04    /* 32bit */
  88 #define CFG_MAX_FLASH_BANKS     (2)
  89 #define CFG_MAX_FLASH_SECT      270
  90 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE,\
  91                         CFG_FLASH_BASE + 0x100000,\
  92                         CFG_FLASH_BASE + 0x400000,\
  93                         CFG_FLASH_BASE + 0x700000, }
  94 #endif /* CONFIG_R2DPLUS_OLD */
  95
  96 #define CFG_ENV_IS_IN_FLASH
  97 #define CFG_ENV_SECT_SIZE       0x20000
  98 #define CFG_ENV_SIZE            (CFG_ENV_SECT_SIZE)
  99 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 100 #define CFG_FLASH_ERASE_TOUT    120000
 101 #define CFG_FLASH_WRITE_TOUT    500
 102
 103 /*
 104  * SuperH Clock setting
 105  */
 106 #define CONFIG_SYS_CLK_FREQ     60000000
 107 #define TMU_CLK_DIVIDER         4
 108 #define CFG_HZ                  (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
 109 #define CFG_PLL_SETTLING_TIME   100/* in us */
 110
 111 /*
 112  * IDE support
 113  */
 114 #define CONFIG_IDE_RESET        1
 115 #define CFG_PIO_MODE            1
 116 #define CFG_IDE_MAXBUS          1 /* IDE bus */
 117 #define CFG_IDE_MAXDEVICE       1
 118 #define CFG_ATA_BASE_ADDR       0xb4000000
 119 #define CFG_ATA_STRIDE          2 /* 1bit shift */
 120 #define CFG_ATA_DATA_OFFSET     0x1000  /* data reg offset */
 121 #define CFG_ATA_REG_OFFSET      0x1000  /* reg offset */
 122 #define CFG_ATA_ALT_OFFSET      0x800   /* alternate register offset */
 123
 124 /*
 125  * SuperH PCI Bridge Configration
 126  */
 127 #define CONFIG_PCI
 128 #define CONFIG_SH4_PCI
 129 #define CONFIG_SH7751_PCI
 130 #define CONFIG_PCI_PNP
 131 #define CONFIG_PCI_SCAN_SHOW    1
 132 #define __io
 133 #define __mem_pci
 134
 135 #define CONFIG_PCI_MEM_BUS      0xFD000000      /* Memory space base addr */
 136 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 137 #define CONFIG_PCI_MEM_SIZE     0x01000000      /* Size of Memory window */
 138 #define CONFIG_PCI_IO_BUS       0xFE240000      /* IO space base address */
 139 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 140 #define CONFIG_PCI_IO_SIZE      0x00040000      /* Size of IO window */
 141
 142 /*
 143  * Network device (RTL8139) support
 144  */
 145 #define CONFIG_NET_MULTI
 146 #define CONFIG_RTL8139
 147 #define _IO_BASE                0x00000000
 148 #define KSEG1ADDR(x)            (x)
 149
 150 #endif /* __CONFIG_H */