include/configs/r2dplus.h

   1 #ifndef __CONFIG_H
   2 #define __CONFIG_H
   3
   4 #undef DEBUG
   5
   6 #define CONFIG_SH               1
   7 #define CONFIG_SH4              1
   8 #define CONFIG_CPU_SH7751       1
   9 #define CONFIG_CPU_SH_TYPE_R    1
  10 #define CONFIG_R2DPLUS          1
  11 #define __LITTLE_ENDIAN__       1
  12
  13 /*
  14  * Command line configuration.
  15  */
  16 #include <config_cmd_default.h>
  17
  18 #define CONFIG_CMD_DFL
  19 #define CONFIG_CMD_CACHE
  20 #define CONFIG_CMD_FLASH
  21 #define CONFIG_CMD_PCI
  22 #define CONFIG_CMD_NET
  23 #define CONFIG_CMD_PING
  24 #define CONFIG_CMD_IDE
  25 #define CONFIG_CMD_EXT2
  26 #define CONFIG_DOS_PARTITION
  27
  28 /* SCIF */
  29 #define CONFIG_SCIF_CONSOLE     1
  30 #define CONFIG_BAUDRATE         115200
  31 #define CONFIG_CONS_SCIF1       1
  32 #define BOARD_LATE_INIT         1
  33
  34 #define CONFIG_BOOTDELAY        -1
  35 #define CONFIG_BOOTARGS         "console=ttySC0,115200"
  36 #define CONFIG_ENV_OVERWRITE    1
  37
  38 /* SDRAM */
  39 #define CFG_SDRAM_BASE          (0x8C000000)
  40 #define CFG_SDRAM_SIZE          (0x04000000)
  41
  42 #define CFG_LONGHELP
  43 #define CFG_PROMPT              "=> "
  44 #define CFG_CBSIZE              256
  45 #define CFG_PBSIZE              256
  46 #define CFG_MAXARGS             16
  47 #define CFG_BARGSIZE            512
  48 /* List of legal baudrate settings for this board */
  49 #define CFG_BAUDRATE_TABLE      { 115200, 57600, 38400, 19200, 9600 }
  50
  51 #define CFG_MEMTEST_START       (CFG_SDRAM_BASE)
  52 #define CFG_MEMTEST_END         (TEXT_BASE - 0x100000)
  53
  54 #define CFG_LOAD_ADDR           (CFG_SDRAM_BASE + 32 * 1024 * 1024)
  55 /* Address of u-boot image in Flash */
  56 #define CFG_MONITOR_BASE        (CFG_FLASH_BASE)
  57 #define CFG_MONITOR_LEN         (256 * 1024)
  58 /* Size of DRAM reserved for malloc() use */
  59 #define CFG_MALLOC_LEN          (1024 * 1024)
  60 /* size in bytes reserved for initial data */
  61 #define CFG_GBL_DATA_SIZE       (256)
  62 #define CFG_BOOTMAPSZ           (8 * 1024 * 1024)
  63
  64 /*
  65  * NOR Flash ( Spantion S29GL256P )
  66  */
  67 #define CFG_FLASH_CFI
  68 #define CONFIG_FLASH_CFI_DRIVER
  69 #define CFG_FLASH_BASE          (0xA0000000)
  70 #define CFG_MAX_FLASH_BANKS (1)
  71 #define CFG_MAX_FLASH_SECT  256
  72 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
  73
  74 #define CFG_ENV_IS_IN_FLASH
  75 #define CFG_ENV_SECT_SIZE       0x40000
  76 #define CFG_ENV_SIZE        (CFG_ENV_SECT_SIZE)
  77 #define CFG_ENV_ADDR        (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  78
  79 /*
  80  * SuperH Clock setting
  81  */
  82 #define CONFIG_SYS_CLK_FREQ     60000000
  83 #define TMU_CLK_DIVIDER         4
  84 #define CFG_HZ                  (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
  85 #define CFG_PLL_SETTLING_TIME   100/* in us */
  86
  87 /*
  88  * IDE support
  89  */
  90 #define CONFIG_IDE_RESET        1
  91 #define CFG_PIO_MODE            1
  92 #define CFG_IDE_MAXBUS          1 /* IDE bus */
  93 #define CFG_IDE_MAXDEVICE       1
  94 #define CFG_ATA_BASE_ADDR       0xb4000000
  95 #define CFG_ATA_STRIDE          2 /* 1bit shift */
  96 #define CFG_ATA_DATA_OFFSET     0x1000  /* data reg offset */
  97 #define CFG_ATA_REG_OFFSET      0x1000  /* reg offset */
  98 #define CFG_ATA_ALT_OFFSET      0x800   /* alternate register offset */
  99
 100 /*
 101  * SuperH PCI Bridge Configration
 102  */
 103 #define CONFIG_PCI
 104 #define CONFIG_SH4_PCI
 105 #define CONFIG_SH7751_PCI
 106 #define CONFIG_PCI_PNP
 107 #define CONFIG_PCI_SCAN_SHOW    1
 108 #define __io
 109 #define __mem_pci
 110
 111 #define CONFIG_PCI_MEM_BUS      0xFD000000      /* Memory space base addr */
 112 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 113 #define CONFIG_PCI_MEM_SIZE     0x01000000      /* Size of Memory window */
 114 #define CONFIG_PCI_IO_BUS       0xFE240000      /* IO space base address */
 115 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 116 #define CONFIG_PCI_IO_SIZE      0x00040000      /* Size of IO window */
 117
 118 /*
 119  * Network device (RTL8139) support
 120  */
 121 #define CONFIG_NET_MULTI
 122 #define CONFIG_RTL8139
 123 #define _IO_BASE                0x00000000
 124 #define KSEG1ADDR(x)            (x)
 125
 126 #endif /* __CONFIG_H */