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1 /*
2 * Configuation settings for the Renesas R7780MP board
3 *
4 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __R7780RP_H
11 #define __R7780RP_H
12
13 #define CONFIG_CPU_SH7780 1
14 #define CONFIG_R7780MP 1
15 #define CONFIG_SYS_R7780MP_OLD_FLASH 1
16 #define __LITTLE_ENDIAN__ 1
17
18 #define CONFIG_DISPLAY_BOARDINFO
19
20 #define CONFIG_CONS_SCIF0 1
21
22 #define CONFIG_ENV_OVERWRITE 1
23
24 #define CONFIG_SYS_SDRAM_BASE (0x08000000)
25 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
26
27 #define CONFIG_SYS_LONGHELP
28 #define CONFIG_SYS_PBSIZE 256
29
30 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
31 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
32
33 /* Flash board support */
34 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
35 #ifdef CONFIG_SYS_R7780MP_OLD_FLASH
36 /* NOR Flash (S29PL127J60TFI130) */
37 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
38 # define CONFIG_SYS_MAX_FLASH_BANKS (2)
39 # define CONFIG_SYS_MAX_FLASH_SECT 270
40 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
41 CONFIG_SYS_FLASH_BASE + 0x100000,\
42 CONFIG_SYS_FLASH_BASE + 0x400000,\
43 CONFIG_SYS_FLASH_BASE + 0x700000, }
44 #else /* CONFIG_SYS_R7780MP_OLD_FLASH */
45 /* NOR Flash (Spantion S29GL256P) */
46 # define CONFIG_SYS_MAX_FLASH_BANKS (1)
47 # define CONFIG_SYS_MAX_FLASH_SECT 256
48 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
49 #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
50
51 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
52 /* Address of u-boot image in Flash */
53 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
54 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
55 /* Size of DRAM reserved for malloc() use */
56 #define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
57
58 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
59 #define CONFIG_SYS_RX_ETH_BUFFER (8)
60
61 #define CONFIG_SYS_FLASH_CFI
62 #define CONFIG_FLASH_CFI_DRIVER
63 #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
64 #undef CONFIG_SYS_FLASH_QUIET_TEST
65 /* print 'E' for empty sector on flinfo */
66 #define CONFIG_SYS_FLASH_EMPTY_INFO
67
68 #define CONFIG_ENV_SECT_SIZE (256 * 1024)
69 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
70 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
71 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000
72 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
73
74 /* Board Clock */
75 #define CONFIG_SYS_CLK_FREQ 33333333
76 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
77 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
78 #define CONFIG_SYS_TMU_CLK_DIV 4
79
80 /* PCI Controller */
81 #if defined(CONFIG_CMD_PCI)
82 #define CONFIG_SH4_PCI
83 #define CONFIG_SH7780_PCI
84 #define CONFIG_SH7780_PCI_LSR 0x07f00001
85 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
86 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
87 #define CONFIG_PCI_SCAN_SHOW 1
88 #define __mem_pci
89
90 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
91 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
92 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
93
94 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
95 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
96 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
97 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
98 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
99 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
100 #endif /* CONFIG_CMD_PCI */
101
102 #if defined(CONFIG_CMD_NET)
103 /* AX88796L Support(NE2000 base chip) */
104 #define CONFIG_DRIVER_AX88796L
105 #define CONFIG_DRIVER_NE2000_BASE 0xA4100000
106 #endif
107
108 /* Compact flash Support */
109 #if defined(CONFIG_IDE)
110 #define CONFIG_IDE_RESET 1
111 #define CONFIG_SYS_PIO_MODE 1
112 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
113 #define CONFIG_SYS_IDE_MAXDEVICE 1
114 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
115 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
116 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
117 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
118 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
119 #define CONFIG_IDE_SWAP_IO
120 #endif /* CONFIG_IDE */
121
122 #endif /* __R7780RP_H */