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[people/ms/u-boot.git] / include / configs / r7780mp.h
1 /*
2 * Configuation settings for the Renesas R7780MP board
3 *
4 * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __R7780RP_H
11 #define __R7780RP_H
12
13 #define CONFIG_CPU_SH7780 1
14 #define CONFIG_R7780MP 1
15 #define CONFIG_SYS_R7780MP_OLD_FLASH 1
16 #define __LITTLE_ENDIAN__ 1
17
18 #define CONFIG_DISPLAY_BOARDINFO
19
20 #define CONFIG_CONS_SCIF0 1
21
22 #define CONFIG_ENV_OVERWRITE 1
23
24 #define CONFIG_SYS_TEXT_BASE 0x0FFC0000
25 #define CONFIG_SYS_SDRAM_BASE (0x08000000)
26 #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
27
28 #define CONFIG_SYS_LONGHELP
29 #define CONFIG_SYS_CBSIZE 256
30 #define CONFIG_SYS_PBSIZE 256
31 #define CONFIG_SYS_MAXARGS 16
32 #define CONFIG_SYS_BARGSIZE 512
33
34 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
35 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
36
37 /* Flash board support */
38 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
39 #ifdef CONFIG_SYS_R7780MP_OLD_FLASH
40 /* NOR Flash (S29PL127J60TFI130) */
41 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
42 # define CONFIG_SYS_MAX_FLASH_BANKS (2)
43 # define CONFIG_SYS_MAX_FLASH_SECT 270
44 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
45 CONFIG_SYS_FLASH_BASE + 0x100000,\
46 CONFIG_SYS_FLASH_BASE + 0x400000,\
47 CONFIG_SYS_FLASH_BASE + 0x700000, }
48 #else /* CONFIG_SYS_R7780MP_OLD_FLASH */
49 /* NOR Flash (Spantion S29GL256P) */
50 # define CONFIG_SYS_MAX_FLASH_BANKS (1)
51 # define CONFIG_SYS_MAX_FLASH_SECT 256
52 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
53 #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */
54
55 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
56 /* Address of u-boot image in Flash */
57 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
58 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
59 /* Size of DRAM reserved for malloc() use */
60 #define CONFIG_SYS_MALLOC_LEN (1204 * 1024)
61
62 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
63 #define CONFIG_SYS_RX_ETH_BUFFER (8)
64
65 #define CONFIG_SYS_FLASH_CFI
66 #define CONFIG_FLASH_CFI_DRIVER
67 #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
68 #undef CONFIG_SYS_FLASH_QUIET_TEST
69 /* print 'E' for empty sector on flinfo */
70 #define CONFIG_SYS_FLASH_EMPTY_INFO
71
72 #define CONFIG_ENV_SECT_SIZE (256 * 1024)
73 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
74 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
75 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000
76 #define CONFIG_SYS_FLASH_WRITE_TOUT 500
77
78 /* Board Clock */
79 #define CONFIG_SYS_CLK_FREQ 33333333
80 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
81 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
82 #define CONFIG_SYS_TMU_CLK_DIV 4
83
84 /* PCI Controller */
85 #if defined(CONFIG_CMD_PCI)
86 #define CONFIG_SH4_PCI
87 #define CONFIG_SH7780_PCI
88 #define CONFIG_SH7780_PCI_LSR 0x07f00001
89 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
90 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
91 #define CONFIG_PCI_SCAN_SHOW 1
92 #define __mem_pci
93
94 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
95 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
96 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
97
98 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
99 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
100 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
101 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
102 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
103 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
104 #endif /* CONFIG_CMD_PCI */
105
106 #if defined(CONFIG_CMD_NET)
107 /* AX88796L Support(NE2000 base chip) */
108 #define CONFIG_DRIVER_AX88796L
109 #define CONFIG_DRIVER_NE2000_BASE 0xA4100000
110 #endif
111
112 /* Compact flash Support */
113 #if defined(CONFIG_IDE)
114 #define CONFIG_IDE_RESET 1
115 #define CONFIG_SYS_PIO_MODE 1
116 #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
117 #define CONFIG_SYS_IDE_MAXDEVICE 1
118 #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
119 #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
120 #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
121 #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
122 #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
123 #define CONFIG_IDE_SWAP_IO
124 #endif /* CONFIG_IDE */
125
126 #endif /* __R7780RP_H */