include/configs/rk3188_common.h

   1 /*
   2  * (C) Copyright 2015 Google, Inc
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_RK3188_COMMON_H
   8 #define __CONFIG_RK3188_COMMON_H
   9
  10 #define CONFIG_SYS_CACHELINE_SIZE       64
  11
  12 #include <asm/arch/hardware.h>
  13 #include "rockchip-common.h"
  14
  15 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  16 #define CONFIG_NR_DRAM_BANKS            1
  17 #define CONFIG_ENV_SIZE                 0x2000
  18 #define CONFIG_SYS_MAXARGS              16
  19 #define CONFIG_SYS_MALLOC_LEN           (32 << 20)
  20 #define CONFIG_SYS_CBSIZE               1024
  21
  22 #define CONFIG_SYS_TIMER_RATE           (24 * 1000 * 1000)
  23 #define CONFIG_SYS_TIMER_BASE           0x2000e000 /* TIMER3 */
  24 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMER_BASE + 8)
  25 #define CONFIG_SYS_TIMER_COUNTS_DOWN
  26
  27 #define CONFIG_SYS_NS16550_MEM32
  28
  29 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
  30 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
  31 #define CONFIG_SYS_TEXT_BASE            0x60000000
  32 #else
  33 #define CONFIG_SYS_TEXT_BASE            0x60100000
  34 #endif
  35 #define CONFIG_SYS_INIT_SP_ADDR         0x60100000
  36 #define CONFIG_SYS_LOAD_ADDR            0x60800800
  37
  38 #define CONFIG_ROCKCHIP_MAX_INIT_SIZE   (0x8000 - 0x800)
  39 #define CONFIG_ROCKCHIP_CHIP_TAG        "RK31"
  40
  41 #ifdef CONFIG_TPL_BUILD
  42 #define CONFIG_SPL_TEXT_BASE            0x10080804
  43 /* tpl size 1kb - 4byte RK31 header */
  44 #define CONFIG_SPL_MAX_SIZE             (0x400 - 0x4)
  45 #elif defined(CONFIG_SPL_BUILD)
  46 /* spl size 32kb sram - 2kb bootrom - 1kb spl */
  47 #define CONFIG_SPL_MAX_SIZE             (0x8000 - 0xC00)
  48 #define CONFIG_SPL_TEXT_BASE            0x10080C00
  49 #define CONFIG_SPL_FRAMEWORK            1
  50 #define CONFIG_SPL_CLK                  1
  51 #define CONFIG_SPL_PINCTRL              1
  52 #define CONFIG_SPL_REGMAP               1
  53 #define CONFIG_SPL_SYSCON               1
  54 #define CONFIG_SPL_RAM                  1
  55 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1
  56 #define CONFIG_ROCKCHIP_SERIAL          1
  57 #endif
  58
  59 #define CONFIG_SPL_STACK                0x10087fff
  60
  61 /* MMC/SD IP block */
  62 #define CONFIG_BOUNCE_BUFFER
  63
  64 #define CONFIG_SYS_SDRAM_BASE           0x60000000
  65 #define CONFIG_NR_DRAM_BANKS            1
  66 #define SDRAM_BANK_SIZE                 (2UL << 30)
  67
  68 #define CONFIG_SPI_FLASH
  69 #define CONFIG_SPI
  70 #define CONFIG_SF_DEFAULT_SPEED 20000000
  71
  72 #ifndef CONFIG_SPL_BUILD
  73 /* usb otg */
  74 #define CONFIG_USB_GADGET
  75 #define CONFIG_USB_GADGET_DUALSPEED
  76 #define CONFIG_USB_GADGET_DWC2_OTG
  77 #define CONFIG_ROCKCHIP_USB2_PHY
  78 #define CONFIG_USB_GADGET_VBUS_DRAW     0
  79
  80 #define CONFIG_USB_GADGET_DOWNLOAD
  81 #define CONFIG_G_DNL_MANUFACTURER       "Rockchip"
  82 #define CONFIG_G_DNL_VENDOR_NUM         0x2207
  83 #define CONFIG_G_DNL_PRODUCT_NUM        0x310a
  84
  85 /* usb host support */
  86 #ifdef CONFIG_CMD_USB
  87 #define CONFIG_USB_DWC2
  88 #define CONFIG_USB_HOST_ETHER
  89 #define CONFIG_USB_ETHER_SMSC95XX
  90 #define CONFIG_USB_ETHER_ASIX
  91 #endif
  92 #define ENV_MEM_LAYOUT_SETTINGS \
  93         "scriptaddr=0x60000000\0" \
  94         "pxefile_addr_r=0x60100000\0" \
  95         "fdt_addr_r=0x61f00000\0" \
  96         "kernel_addr_r=0x62000000\0" \
  97         "ramdisk_addr_r=0x64000000\0"
  98
  99 #include <config_distro_bootcmd.h>
 100
 101 /* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
 102  * so limit the fdt reallocation to that */
 103 #define CONFIG_EXTRA_ENV_SETTINGS \
 104         "fdt_high=0x6fffffff\0" \
 105         "initrd_high=0x6fffffff\0" \
 106         "partitions=" PARTS_DEFAULT \
 107         ENV_MEM_LAYOUT_SETTINGS \
 108         ROCKCHIP_DEVICE_SETTINGS \
 109         BOOTENV
 110
 111 #endif /* CONFIG_SPL_BUILD */
 112
 113 #define CONFIG_PREBOOT
 114
 115 #endif