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1 /*
2 * Configuation settings for the Renesas RSK2+SH7264 board
3 *
4 * Copyright (C) 2011 Renesas Electronics Europe Ltd.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 * Copyright (C) 2008 Renesas Solutions Corp.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #ifndef __RSK7264_H
12 #define __RSK7264_H
13
14 #define CONFIG_CPU_SH7264 1
15 #define CONFIG_RSK7264 1
16
17 #define CONFIG_DISPLAY_BOARDINFO
18
19 #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
20
21 #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
22 #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
23 #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
24 #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
25
26 /* Serial */
27 #define CONFIG_CONS_SCIF3 1
28
29 /* Memory */
30 /* u-boot relocated to top 256KB of ram */
31 #define CONFIG_SYS_TEXT_BASE 0x0CFC0000
32 #define CONFIG_SYS_SDRAM_BASE 0x0C000000
33 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
34
35 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
36 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
37 #define CONFIG_SYS_MALLOC_LEN (256 * 1024)
38 #define CONFIG_SYS_MONITOR_LEN (128 * 1024)
39 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
40
41 /* Flash */
42 #define CONFIG_FLASH_CFI_DRIVER
43 #define CONFIG_SYS_FLASH_CFI
44 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
45 #define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
46 #define CONFIG_SYS_MAX_FLASH_BANKS 1
47 #define CONFIG_SYS_MAX_FLASH_SECT 512
48
49 #define CONFIG_ENV_OFFSET (128 * 1024)
50 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
51 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
52 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
53
54 /* Board Clock */
55 #define CONFIG_SYS_CLK_FREQ 36000000
56 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
57 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
58 #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
59 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
60
61 /* Network interface */
62 #define CONFIG_SMC911X
63 #define CONFIG_SMC911X_16_BIT
64 #define CONFIG_SMC911X_BASE 0x28000000
65
66 #endif /* __RSK7264_H */