include/configs/sacsng.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * (C) Copyright 2000
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * (C) Copyright 2001
  10  * Advent Networks, Inc. <http://www.adventnetworks.com>
  11  * Jay Monkman <jtm@smoothsmoothie.com>
  12  *
  13  * Configuration settings for the WindRiver SBC8260 board.
  14  *      See http://www.windriver.com/products/html/sbc8260.html
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /* Enable debug prints */
  39 #undef DEBUG                  /* General debug */
  40 #undef DEBUG_BOOTP_EXT        /* Debug received vendor fields */
  41
  42 /*****************************************************************************
  43  *
  44  * These settings must match the way _your_ board is set up
  45  *
  46  *****************************************************************************/
  47
  48 /* What is the oscillator's (UX2) frequency in Hz? */
  49 #define CONFIG_8260_CLKIN  66666600
  50
  51 /*-----------------------------------------------------------------------
  52  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  53  *-----------------------------------------------------------------------
  54  * What should MODCK_H be? It is dependent on the oscillator
  55  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  56  * Here are some example values (all frequencies are in MHz):
  57  *
  58  * MODCK_H   MODCK[1-3]  Osc    CPM    Core  S2-6   S2-7   S2-8
  59  * -------   ----------  ---    ---    ----  -----  -----  -----
  60  * 0x1       0x5         33     100    133   Open   Close  Open
  61  * 0x1       0x6         33     100    166   Open   Open   Close
  62  * 0x1       0x7         33     100    200   Open   Open   Open
  63  *
  64  * 0x2       0x2         33     133    133   Close  Open   Close
  65  * 0x2       0x3         33     133    166   Close  Open   Open
  66  * 0x2       0x4         33     133    200   Open   Close  Close
  67  * 0x2       0x5         33     133    233   Open   Close  Open
  68  * 0x2       0x6         33     133    266   Open   Open   Close
  69  *
  70  * 0x5       0x5         66     133    133   Open   Close  Open
  71  * 0x5       0x6         66     133    166   Open   Open   Close
  72  * 0x5       0x7         66     133    200   Open   Open   Open
  73  * 0x6       0x0         66     133    233   Close  Close  Close
  74  * 0x6       0x1         66     133    266   Close  Close  Open
  75  * 0x6       0x2         66     133    300   Close  Open   Close
  76  */
  77 #define CFG_SBC_MODCK_H 0x05
  78
  79 /* Define this if you want to boot from 0x00000100. If you don't define
  80  * this, you will need to program the bootloader to 0xfff00000, and
  81  * get the hardware reset config words at 0xfe000000. The simplest
  82  * way to do that is to program the bootloader at both addresses.
  83  * It is suggested that you just let U-Boot live at 0x00000000.
  84  */
  85 #define CFG_SBC_BOOT_LOW 1
  86
  87 /* What should the base address of the main FLASH be and how big is
  88  * it (in MBytes)?  This must contain TEXT_BASE from board/sacsng/config.mk
  89  * The main FLASH is whichever is connected to *CS0.
  90  */
  91 #define CFG_FLASH0_BASE 0x40000000
  92 #define CFG_FLASH0_SIZE 2
  93
  94 /* What should the base address of the secondary FLASH be and how big
  95  * is it (in Mbytes)?  The secondary FLASH is whichever is connected
  96  * to *CS6.
  97  */
  98 #define CFG_FLASH1_BASE 0x60000000
  99 #define CFG_FLASH1_SIZE 2
 100
 101 /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
 102  */
 103 #define CONFIG_VERY_BIG_RAM     1
 104
 105 /* What should be the base address of SDRAM DIMM and how big is
 106  * it (in Mbytes)?  This will normally auto-configure via the SPD.
 107 */
 108 #define CFG_SDRAM0_BASE 0x00000000
 109 #define CFG_SDRAM0_SIZE 64
 110
 111 /*
 112  * Memory map example with 64 MB DIMM:
 113  *
 114  *     0x0000 0000     Exception Vector code, 8k
 115  *           :
 116  *     0x0000 1FFF
 117  *     0x0000 2000     Free for Application Use
 118  *           :
 119  *           :
 120  *
 121  *           :
 122  *           :
 123  *     0x03F5 FF30     Monitor Stack (Growing downward)
 124  *                     Monitor Stack Buffer (0x80)
 125  *     0x03F5 FFB0     Board Info Data
 126  *     0x03F6 0000     Malloc Arena
 127  *           :              CFG_ENV_SECT_SIZE, 16k
 128  *           :              CFG_MALLOC_LEN,    128k
 129  *     0x03FC 0000     RAM Copy of Monitor Code
 130  *           :              CFG_MONITOR_LEN,   256k
 131  *     0x03FF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
 132  */
 133
 134 #define CONFIG_POST             (CFG_POST_MEMORY | \
 135                                  CFG_POST_CPU)
 136
 137
 138 /*
 139  * select serial console configuration
 140  *
 141  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 142  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 143  * for SCC).
 144  *
 145  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 146  * defined elsewhere.
 147  */
 148 #define CONFIG_CONS_ON_SMC      1       /* define if console on SMC */
 149 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 150 #undef  CONFIG_CONS_NONE                /* define if console on neither */
 151 #define CONFIG_CONS_INDEX       1       /* which SMC/SCC channel for console */
 152
 153 /*
 154  * select ethernet configuration
 155  *
 156  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 157  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 158  * for FCC)
 159  *
 160  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 161  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 162  * from CONFIG_COMMANDS to remove support for networking.
 163  */
 164
 165 #undef  CONFIG_ETHER_ON_SCC
 166 #define CONFIG_ETHER_ON_FCC
 167 #undef  CONFIG_ETHER_NONE               /* define if ethernet on neither */
 168
 169 #ifdef  CONFIG_ETHER_ON_SCC
 170 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
 171 #endif  /* CONFIG_ETHER_ON_SCC */
 172
 173 #ifdef  CONFIG_ETHER_ON_FCC
 174 #define CONFIG_ETHER_INDEX      2       /* which SCC/FCC channel for ethernet */
 175 #define CONFIG_MII                      /* MII PHY management           */
 176 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 177 /*
 178  * Port pins used for bit-banged MII communictions (if applicable).
 179  */
 180
 181 #define MDIO_PORT       2               /* Port A=0, B=1, C=2, D=3 */
 182 #define MDIO_ACTIVE     (iop->pdir |=  0x40000000)
 183 #define MDIO_TRISTATE   (iop->pdir &= ~0x40000000)
 184 #define MDIO_READ       ((iop->pdat &  0x40000000) != 0)
 185
 186 #define MDIO(bit)       if(bit) iop->pdat |=  0x40000000; \
 187                         else    iop->pdat &= ~0x40000000
 188
 189 #define MDC(bit)        if(bit) iop->pdat |=  0x80000000; \
 190                         else    iop->pdat &= ~0x80000000
 191
 192 #define MIIDELAY        udelay(50)
 193 #endif  /* CONFIG_ETHER_ON_FCC */
 194
 195 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 196
 197 /*
 198  *  - RX clk is CLK11
 199  *  - TX clk is CLK12
 200  */
 201 # define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  | CMXSCR_TS1CS_CLK12)
 202
 203 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 204
 205 /*
 206  * - Rx-CLK is CLK13
 207  * - Tx-CLK is CLK14
 208  * - Select bus for bd/buffers (see 28-13)
 209  * - Enable Full Duplex in FSMR
 210  */
 211 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 212 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 213 # define CFG_CPMFCR_RAMTYPE     0
 214 # define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
 215
 216 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 217
 218 #define CONFIG_SHOW_BOOT_PROGRESS 1     /* boot progress enabled        */
 219
 220 /*
 221  * Configure for RAM tests.
 222  */
 223 #undef  CFG_DRAM_TEST                   /* calls other tests in board.c */
 224
 225
 226 /*
 227  * Status LED for power up status feedback.
 228  */
 229 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
 230
 231 #define STATUS_LED_PAR          im_ioport.iop_ppara
 232 #define STATUS_LED_DIR          im_ioport.iop_pdira
 233 #define STATUS_LED_ODR          im_ioport.iop_podra
 234 #define STATUS_LED_DAT          im_ioport.iop_pdata
 235
 236 #define STATUS_LED_BIT          0x00000800      /* LED 0 is on PA.20    */
 237 #define STATUS_LED_PERIOD       (CFG_HZ)
 238 #define STATUS_LED_STATE        STATUS_LED_OFF
 239 #define STATUS_LED_BIT1         0x00001000      /* LED 1 is on PA.19    */
 240 #define STATUS_LED_PERIOD1      (CFG_HZ)
 241 #define STATUS_LED_STATE1       STATUS_LED_OFF
 242 #define STATUS_LED_BIT2         0x00002000      /* LED 2 is on PA.18    */
 243 #define STATUS_LED_PERIOD2      (CFG_HZ/2)
 244 #define STATUS_LED_STATE2       STATUS_LED_ON
 245
 246 #define STATUS_LED_ACTIVE       0               /* LED on for bit == 0  */
 247
 248 #define STATUS_LED_YELLOW       0
 249 #define STATUS_LED_GREEN        1
 250 #define STATUS_LED_RED          2
 251 #define STATUS_LED_BOOT         1
 252
 253
 254 /*
 255  * Select SPI support configuration
 256  */
 257 #define CONFIG_SOFT_SPI         /* Enable SPI driver */
 258 #define MAX_SPI_BYTES   4       /* Maximum number of bytes we can handle */
 259 #undef  DEBUG_SPI               /* Disable SPI debugging */
 260
 261 /*
 262  * Software (bit-bang) SPI driver configuration
 263  */
 264 #ifdef CONFIG_SOFT_SPI
 265
 266 /*
 267  * Software (bit-bang) SPI driver configuration
 268  */
 269 #define I2C_SCLK        0x00002000      /* PD 18: Shift clock */
 270 #define I2C_MOSI        0x00004000      /* PD 17: Master Out, Slave In */
 271 #define I2C_MISO        0x00008000      /* PD 16: Master In, Slave Out */
 272
 273 #undef  SPI_INIT                        /* no port initialization needed */
 274 #define SPI_READ        ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
 275 #define SPI_SDA(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_MOSI; \
 276                         else    immr->im_ioport.iop_pdatd &= ~I2C_MOSI
 277 #define SPI_SCL(bit)    if(bit) immr->im_ioport.iop_pdatd |=  I2C_SCLK; \
 278                         else    immr->im_ioport.iop_pdatd &= ~I2C_SCLK
 279 #define SPI_DELAY                       /* No delay is needed */
 280 #endif /* CONFIG_SOFT_SPI */
 281
 282
 283 /*
 284  * select I2C support configuration
 285  *
 286  * Supported configurations are {none, software, hardware} drivers.
 287  * If the software driver is chosen, there are some additional
 288  * configuration items that the driver uses to drive the port pins.
 289  */
 290 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 291 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 292 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 293 #define CFG_I2C_SLAVE           0x7F
 294
 295 /*
 296  * Software (bit-bang) I2C driver configuration
 297  */
 298 #ifdef CONFIG_SOFT_I2C
 299 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 300 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 301 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 302 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 303 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 304                         else    iop->pdat &= ~0x00010000
 305 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 306                         else    iop->pdat &= ~0x00020000
 307 #define I2C_DELAY       udelay(20)      /* 1/4 I2C clock duration */
 308 #endif /* CONFIG_SOFT_I2C */
 309
 310 /* Define this to reserve an entire FLASH sector for
 311  * environment variables. Otherwise, the environment will be
 312  * put in the same sector as U-Boot, and changing variables
 313  * will erase U-Boot temporarily
 314  */
 315 #define CFG_ENV_IN_OWN_SECT     1
 316
 317 /* Define this to contain any number of null terminated strings that
 318  * will be part of the default enviroment compiled into the boot image.
 319  */
 320 #define CONFIG_EXTRA_ENV_SETTINGS \
 321 "serverip=192.168.123.201\0" \
 322 "ipaddr=192.168.123.203\0" \
 323 "checkhostname=VR8500\0" \
 324 "reprog="\
 325     "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
 326     "protect off 60000000 6003FFFF; " \
 327     "erase 60000000 6003FFFF; " \
 328     "cp.b 140000 60000000 $(filesize); " \
 329     "protect on 60000000 6003FFFF\0" \
 330 "copyenv="\
 331     "protect off 60040000 6004FFFF; " \
 332     "erase 60040000 6004FFFF; " \
 333     "cp.b 40040000 60040000 10000; " \
 334     "protect on 60040000 6004FFFF\0" \
 335 "copyprog="\
 336     "protect off 60000000 6003FFFF; " \
 337     "erase 60000000 6003FFFF; " \
 338     "cp.b 40000000 60000000 40000; " \
 339     "protect on 60000000 6003FFFF\0" \
 340 "zapenv="\
 341     "protect off 40040000 4004FFFF; " \
 342     "erase 40040000 4004FFFF; " \
 343     "protect on 40040000 4004FFFF\0" \
 344 "zapotherenv="\
 345     "protect off 60040000 6004FFFF; " \
 346     "erase 60040000 6004FFFF; " \
 347     "protect on 60040000 6004FFFF\0" \
 348 "root-on-initrd="\
 349     "setenv bootcmd "\
 350     "version\\;" \
 351     "echo\\;" \
 352     "bootp\\;" \
 353     "setenv bootargs root=/dev/ram0 rw quiet " \
 354     "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
 355     "run boot-hook\\;" \
 356     "bootm\0" \
 357 "root-on-initrd-debug="\
 358     "setenv bootcmd "\
 359     "version\\;" \
 360     "echo\\;" \
 361     "bootp\\;" \
 362     "setenv bootargs root=/dev/ram0 rw debug " \
 363     "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
 364     "run debug-hook\\;" \
 365     "run boot-hook\\;" \
 366     "bootm\0" \
 367 "root-on-nfs="\
 368     "setenv bootcmd "\
 369     "version\\;" \
 370     "echo\\;" \
 371     "bootp\\;" \
 372     "setenv bootargs root=/dev/nfs rw quiet " \
 373     "nfsroot=\\$(serverip):\\$(rootpath) " \
 374     "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
 375     "run boot-hook\\;" \
 376     "bootm\0" \
 377 "root-on-nfs-debug="\
 378     "setenv bootcmd "\
 379     "version\\;" \
 380     "echo\\;" \
 381     "bootp\\;" \
 382     "setenv bootargs root=/dev/nfs rw debug " \
 383     "nfsroot=\\$(serverip):\\$(rootpath) " \
 384     "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
 385     "run debug-hook\\;" \
 386     "run boot-hook\\;" \
 387     "bootm\0" \
 388 "debug-checkout="\
 389     "setenv checkhostname;" \
 390     "setenv ethaddr 00:09:70:00:00:01;" \
 391     "bootp;" \
 392     "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) debug " \
 393     "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
 394     "run debug-hook;" \
 395     "run boot-hook;" \
 396     "bootm\0" \
 397 "debug-hook="\
 398     "echo ipaddr    $(ipaddr);" \
 399     "echo serverip  $(serverip);" \
 400     "echo gatewayip $(gatewayip);" \
 401     "echo netmask   $(netmask);" \
 402     "echo hostname  $(hostname)\0" \
 403 "ana=run adc ; run dac\0" \
 404 "adc=run adc-12 ; run adc-34\0" \
 405 "adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
 406 "adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
 407 "dac=echo ### DAC ; imd.b 11 81 5\0" \
 408 "boot-hook=run ana\0"
 409
 410 /* What should the console's baud rate be? */
 411 #define CONFIG_BAUDRATE         9600
 412
 413 /* Ethernet MAC address */
 414 #define CONFIG_ETHADDR          00:09:70:00:00:00
 415
 416 /* The default Ethernet MAC address can be overwritten just once  */
 417 #ifdef  CONFIG_ETHADDR
 418 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1
 419 #endif
 420
 421 /*
 422  * Define this to do some miscellaneous board-specific initialization.
 423  */
 424 #define CONFIG_MISC_INIT_R
 425
 426 /* Set to a positive value to delay for running BOOTCOMMAND */
 427 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 428
 429 /* Be selective on what keys can delay or stop the autoboot process
 430  *     To stop  use: " "
 431  */
 432 #define CONFIG_AUTOBOOT_KEYED
 433 #define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
 434 #define CONFIG_AUTOBOOT_STOP_STR        " "
 435 #undef  CONFIG_AUTOBOOT_DELAY_STR
 436 #define CONFIG_ZERO_BOOTDELAY_CHECK
 437 #define DEBUG_BOOTKEYS          0
 438
 439 /* Define a command string that is automatically executed when no character
 440  * is read on the console interface withing "Boot Delay" after reset.
 441  */
 442 #define CONFIG_BOOT_ROOT_INITRD 0       /* Use ram disk for the root file system */
 443 #define CONFIG_BOOT_ROOT_NFS    1       /* Use a NFS mounted root file system */
 444
 445 #if CONFIG_BOOT_ROOT_INITRD
 446 #define CONFIG_BOOTCOMMAND \
 447         "version;" \
 448         "echo;" \
 449         "bootp;" \
 450         "setenv bootargs root=/dev/ram0 rw quiet " \
 451         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
 452         "run boot-hook;" \
 453         "bootm"
 454 #endif /* CONFIG_BOOT_ROOT_INITRD */
 455
 456 #if CONFIG_BOOT_ROOT_NFS
 457 #define CONFIG_BOOTCOMMAND \
 458         "version;" \
 459         "echo;" \
 460         "bootp;" \
 461         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) quiet " \
 462         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
 463         "run boot-hook;" \
 464         "bootm"
 465 #endif /* CONFIG_BOOT_ROOT_NFS */
 466
 467 #define CONFIG_BOOTP_RANDOM_DELAY       /* Randomize the BOOTP retry delay */
 468
 469 #define CONFIG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
 470
 471 /* Add support for a few extra bootp options like:
 472  *      - File size
 473  *      - DNS
 474  */
 475 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | \
 476                                  CONFIG_BOOTP_BOOTFILESIZE | \
 477                                  CONFIG_BOOTP_DNS)
 478
 479 /* undef this to save memory */
 480 #define CFG_LONGHELP
 481
 482 /* Monitor Command Prompt */
 483 #define CFG_PROMPT              "=> "
 484
 485 #undef  CFG_HUSH_PARSER
 486 #ifdef  CFG_HUSH_PARSER
 487 #define CFG_PROMPT_HUSH_PS2     "> "
 488 #endif
 489
 490 /* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
 491  * of an image is printed by image commands like bootm or iminfo.
 492  */
 493 #define CONFIG_TIMESTAMP
 494
 495 /* What U-Boot subsytems do you want enabled? */
 496 #ifdef CONFIG_ETHER_ON_FCC
 497 # define CONFIG_COMMANDS        (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
 498                                 CFG_CMD_ELF     | \
 499                                 CFG_CMD_ASKENV  | \
 500                                 CFG_CMD_ECHO    | \
 501                                 CFG_CMD_I2C     | \
 502                                 CFG_CMD_SPI     | \
 503                                 CFG_CMD_SDRAM   | \
 504                                 CFG_CMD_REGINFO | \
 505                                 CFG_CMD_IMMAP   | \
 506                                 CFG_CMD_MII     )
 507 #else
 508 # define CONFIG_COMMANDS        (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
 509                                 CFG_CMD_ELF     | \
 510                                 CFG_CMD_ASKENV  | \
 511                                 CFG_CMD_ECHO    | \
 512                                 CFG_CMD_I2C     | \
 513                                 CFG_CMD_SPI     | \
 514                                 CFG_CMD_SDRAM   | \
 515                                 CFG_CMD_REGINFO | \
 516                                 CFG_CMD_IMMAP   )
 517 #endif /* CONFIG_ETHER_ON_FCC */
 518
 519 /* Where do the internal registers live? */
 520 #define CFG_IMMR                0xF0000000
 521
 522 /*****************************************************************************
 523  *
 524  * You should not have to modify any of the following settings
 525  *
 526  *****************************************************************************/
 527
 528 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 529 #define CONFIG_SBC8260          1       /* on an EST SBC8260 Board  */
 530 #define CONFIG_SACSng           1       /* munged for the SACSng */
 531
 532 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 533 #include <cmd_confdefs.h>
 534
 535 /*
 536  * Miscellaneous configurable options
 537  */
 538 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 539 #  define CFG_CBSIZE            1024    /* Console I/O Buffer Size           */
 540 #else
 541 #  define CFG_CBSIZE            256     /* Console I/O Buffer Size           */
 542 #endif
 543
 544 /* Print Buffer Size */
 545 #define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
 546
 547 #define CFG_MAXARGS             32      /* max number of command args   */
 548
 549 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size    */
 550
 551 #define CFG_LOAD_ADDR           0x400000   /* default load address */
 552 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 553
 554 #define CFG_ALT_MEMTEST                 /* Select full-featured memory test */
 555 #define CFG_MEMTEST_START       0x2000  /* memtest works from the end of */
 556                                         /* the exception vector table */
 557                                         /* to the end of the DRAM  */
 558                                         /* less monitor and malloc area */
 559 #define CFG_STACK_USAGE         0x10000 /* Reserve 64k for the stack usage */
 560 #define CFG_MEM_END_USAGE       ( CFG_MONITOR_LEN \
 561                                 + CFG_MALLOC_LEN \
 562                                 + CFG_ENV_SECT_SIZE \
 563                                 + CFG_STACK_USAGE )
 564
 565 #define CFG_MEMTEST_END         ( CFG_SDRAM_SIZE * 1024 * 1024 \
 566                                 - CFG_MEM_END_USAGE )
 567
 568 /* valid baudrates */
 569 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 570
 571 /*
 572  * Low Level Configuration Settings
 573  * (address mappings, register initial values, etc.)
 574  * You should know what you are doing if you make changes here.
 575  */
 576
 577 #define CFG_FLASH_BASE  CFG_FLASH0_BASE
 578 #define CFG_FLASH_SIZE  CFG_FLASH0_SIZE
 579 #define CFG_SDRAM_BASE  CFG_SDRAM0_BASE
 580 #define CFG_SDRAM_SIZE  CFG_SDRAM0_SIZE
 581
 582 /*-----------------------------------------------------------------------
 583  * Hard Reset Configuration Words
 584  */
 585 #if defined(CFG_SBC_BOOT_LOW)
 586 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 587 #else
 588 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (0)
 589 #endif /* defined(CFG_SBC_BOOT_LOW) */
 590
 591 /* get the HRCW ISB field from CFG_IMMR */
 592 #define CFG_SBC_HRCW_IMMR       ( ((CFG_IMMR & 0x10000000) >> 10) | \
 593                                   ((CFG_IMMR & 0x01000000) >>  7) | \
 594                                   ((CFG_IMMR & 0x00100000) >>  4) )
 595
 596 #define CFG_HRCW_MASTER         ( HRCW_BPS10                            | \
 597                                   HRCW_DPPC11                           | \
 598                                   CFG_SBC_HRCW_IMMR                     | \
 599                                   HRCW_MMR00                            | \
 600                                   HRCW_LBPC11                           | \
 601                                   HRCW_APPC10                           | \
 602                                   HRCW_CS10PC00                         | \
 603                                   (CFG_SBC_MODCK_H & HRCW_MODCK_H1111)  | \
 604                                   CFG_SBC_HRCW_BOOT_FLAGS )
 605
 606 /* no slaves */
 607 #define CFG_HRCW_SLAVE1         0
 608 #define CFG_HRCW_SLAVE2         0
 609 #define CFG_HRCW_SLAVE3         0
 610 #define CFG_HRCW_SLAVE4         0
 611 #define CFG_HRCW_SLAVE5         0
 612 #define CFG_HRCW_SLAVE6         0
 613 #define CFG_HRCW_SLAVE7         0
 614
 615 /*-----------------------------------------------------------------------
 616  * Definitions for initial stack pointer and data area (in DPRAM)
 617  */
 618 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 619 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 620 #define CFG_GBL_DATA_SIZE       128     /* bytes reserved for initial data */
 621 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 622 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 623
 624 /*-----------------------------------------------------------------------
 625  * Start addresses for the final memory configuration
 626  * (Set up by the startup code)
 627  * Please note that CFG_SDRAM_BASE _must_ start at 0
 628  * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
 629  */
 630 #define CFG_MONITOR_BASE        CFG_FLASH0_BASE
 631
 632 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 633 #  define CFG_RAMBOOT
 634 #endif
 635
 636 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 637 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 638
 639 /*
 640  * For booting Linux, the board info and command line data
 641  * have to be in the first 8 MB of memory, since this is
 642  * the maximum mapped by the Linux kernel during initialization.
 643  */
 644 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 645
 646 /*-----------------------------------------------------------------------
 647  * FLASH and environment organization
 648  */
 649
 650 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant              */
 651 #undef  CFG_FLASH_PROTECTION            /* use hardware protection              */
 652 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 653 #define CFG_MAX_FLASH_SECT      (64+4)  /* max number of sectors on one chip    */
 654
 655 #define CFG_FLASH_ERASE_TOUT    8000    /* Timeout for Flash Erase (in ms)      */
 656 #define CFG_FLASH_WRITE_TOUT    1       /* Timeout for Flash Write (in ms)      */
 657
 658 #ifndef CFG_RAMBOOT
 659 #  define CFG_ENV_IS_IN_FLASH   1
 660
 661 #  ifdef CFG_ENV_IN_OWN_SECT
 662 #    define CFG_ENV_ADDR        (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 663 #    define CFG_ENV_SECT_SIZE   0x10000
 664 #  else
 665 #    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
 666 #    define CFG_ENV_SIZE        0x1000  /* Total Size of Environment Sector     */
 667 #    define CFG_ENV_SECT_SIZE   0x10000 /* see README - env sect real size      */
 668 #  endif /* CFG_ENV_IN_OWN_SECT */
 669
 670 #else
 671 #  define CFG_ENV_IS_IN_NVRAM   1
 672 #  define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 673 #  define CFG_ENV_SIZE          0x200
 674 #endif /* CFG_RAMBOOT */
 675
 676 /*-----------------------------------------------------------------------
 677  * Cache Configuration
 678  */
 679 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 680
 681 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 682 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 683 #endif
 684
 685 /*-----------------------------------------------------------------------
 686  * HIDx - Hardware Implementation-dependent Registers                    2-11
 687  *-----------------------------------------------------------------------
 688  * HID0 also contains cache control - initially enable both caches and
 689  * invalidate contents, then the final state leaves only the instruction
 690  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 691  * but Soft reset does not.
 692  *
 693  * HID1 has only read-only information - nothing to set.
 694  */
 695 #define CFG_HID0_INIT   (HID0_ICE  |\
 696                          HID0_DCE  |\
 697                          HID0_ICFI |\
 698                          HID0_DCI  |\
 699                          HID0_IFEM |\
 700                          HID0_ABE)
 701
 702 #define CFG_HID0_FINAL  (HID0_ICE  |\
 703                          HID0_IFEM |\
 704                          HID0_ABE  |\
 705                          HID0_EMCP)
 706 #define CFG_HID2        0
 707
 708 /*-----------------------------------------------------------------------
 709  * RMR - Reset Mode Register
 710  *-----------------------------------------------------------------------
 711  */
 712 #define CFG_RMR         0
 713
 714 /*-----------------------------------------------------------------------
 715  * BCR - Bus Configuration                                       4-25
 716  *-----------------------------------------------------------------------
 717  */
 718 #define CFG_BCR         (BCR_ETM)
 719
 720 /*-----------------------------------------------------------------------
 721  * SIUMCR - SIU Module Configuration                             4-31
 722  *-----------------------------------------------------------------------
 723  */
 724
 725 #define CFG_SIUMCR      (SIUMCR_DPPC11  |\
 726                          SIUMCR_L2CPC00 |\
 727                          SIUMCR_APPC10  |\
 728                          SIUMCR_MMR00)
 729
 730
 731 /*-----------------------------------------------------------------------
 732  * SYPCR - System Protection Control                            11-9
 733  * SYPCR can only be written once after reset!
 734  *-----------------------------------------------------------------------
 735  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 736  */
 737 #define CFG_SYPCR       (SYPCR_SWTC |\
 738                          SYPCR_BMT  |\
 739                          SYPCR_PBME |\
 740                          SYPCR_LBME |\
 741                          SYPCR_SWRI |\
 742                          SYPCR_SWP)
 743
 744 /*-----------------------------------------------------------------------
 745  * TMCNTSC - Time Counter Status and Control                     4-40
 746  *-----------------------------------------------------------------------
 747  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 748  * and enable Time Counter
 749  */
 750 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
 751                          TMCNTSC_ALR |\
 752                          TMCNTSC_TCF |\
 753                          TMCNTSC_TCE)
 754
 755 /*-----------------------------------------------------------------------
 756  * PISCR - Periodic Interrupt Status and Control                 4-42
 757  *-----------------------------------------------------------------------
 758  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 759  * Periodic timer
 760  */
 761 #define CFG_PISCR       (PISCR_PS  |\
 762                          PISCR_PTF |\
 763                          PISCR_PTE)
 764
 765 /*-----------------------------------------------------------------------
 766  * SCCR - System Clock Control                                   9-8
 767  *-----------------------------------------------------------------------
 768  */
 769 #define CFG_SCCR        0
 770
 771 /*-----------------------------------------------------------------------
 772  * RCCR - RISC Controller Configuration                         13-7
 773  *-----------------------------------------------------------------------
 774  */
 775 #define CFG_RCCR        0
 776
 777 /*
 778  * Initialize Memory Controller:
 779  *
 780  * Bank Bus     Machine PortSz  Device
 781  * ---- ---     ------- ------  ------
 782  *  0   60x     GPCM    16 bit  FLASH (primary flash - 2MB)
 783  *  1   60x     GPCM    -- bit  (Unused)
 784  *  2   60x     SDRAM   64 bit  SDRAM (DIMM)
 785  *  3   60x     SDRAM   64 bit  SDRAM (DIMM)
 786  *  4   60x     GPCM    -- bit  (Unused)
 787  *  5   60x     GPCM    -- bit  (Unused)
 788  *  6   60x     GPCM    16 bit  FLASH  (secondary flash - 2MB)
 789  */
 790
 791 /*-----------------------------------------------------------------------
 792  * BR0,BR1 - Base Register
 793  *     Ref: Section 10.3.1 on page 10-14
 794  * OR0,OR1 - Option Register
 795  *     Ref: Section 10.3.2 on page 10-18
 796  *-----------------------------------------------------------------------
 797  */
 798
 799 /* Bank 0 - Primary FLASH
 800  */
 801
 802 /* BR0 is configured as follows:
 803  *
 804  *     - Base address of 0x40000000
 805  *     - 16 bit port size
 806  *     - Data errors checking is disabled
 807  *     - Read and write access
 808  *     - GPCM 60x bus
 809  *     - Access are handled by the memory controller according to MSEL
 810  *     - Not used for atomic operations
 811  *     - No data pipelining is done
 812  *     - Valid
 813  */
 814 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
 815                          BRx_PS_16                      |\
 816                          BRx_MS_GPCM_P                  |\
 817                          BRx_V)
 818
 819 /* OR0 is configured as follows:
 820  *
 821  *     - 4 MB
 822  *     - *BCTL0 is asserted upon access to the current memory bank
 823  *     - *CW / *WE are negated a quarter of a clock earlier
 824  *     - *CS is output at the same time as the address lines
 825  *     - Uses a clock cycle length of 5
 826  *     - *PSDVAL is generated internally by the memory controller
 827  *       unless *GTA is asserted earlier externally.
 828  *     - Relaxed timing is generated by the GPCM for accesses
 829  *       initiated to this memory region.
 830  *     - One idle clock is inserted between a read access from the
 831  *       current bank and the next access.
 832  */
 833 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
 834                          ORxG_CSNT                      |\
 835                          ORxG_ACS_DIV1                  |\
 836                          ORxG_SCY_5_CLK                 |\
 837                          ORxG_TRLX                      |\
 838                          ORxG_EHTR)
 839
 840 /*-----------------------------------------------------------------------
 841  * BR2,BR3 - Base Register
 842  *     Ref: Section 10.3.1 on page 10-14
 843  * OR2,OR3 - Option Register
 844  *     Ref: Section 10.3.2 on page 10-16
 845  *-----------------------------------------------------------------------
 846  */
 847
 848 /* Bank 2,3 - SDRAM DIMM
 849  */
 850
 851 /* The BR2 is configured as follows:
 852  *
 853  *     - Base address of 0x00000000
 854  *     - 64 bit port size (60x bus only)
 855  *     - Data errors checking is disabled
 856  *     - Read and write access
 857  *     - SDRAM 60x bus
 858  *     - Access are handled by the memory controller according to MSEL
 859  *     - Not used for atomic operations
 860  *     - No data pipelining is done
 861  *     - Valid
 862  */
 863 #define CFG_BR2_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 864                          BRx_PS_64                      |\
 865                          BRx_MS_SDRAM_P                 |\
 866                          BRx_V)
 867
 868 #define CFG_BR3_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 869                          BRx_PS_64                      |\
 870                          BRx_MS_SDRAM_P                 |\
 871                          BRx_V)
 872
 873 /* With a 64 MB DIMM, the OR2 is configured as follows:
 874  *
 875  *     - 64 MB
 876  *     - 4 internal banks per device
 877  *     - Row start address bit is A8 with PSDMR[PBI] = 0
 878  *     - 12 row address lines
 879  *     - Back-to-back page mode
 880  *     - Internal bank interleaving within save device enabled
 881  */
 882 #if (CFG_SDRAM0_SIZE == 64)
 883 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
 884                          ORxS_BPD_4                     |\
 885                          ORxS_ROWST_PBI0_A8             |\
 886                          ORxS_NUMR_12)
 887 #else
 888 #error "INVALID SDRAM CONFIGURATION"
 889 #endif
 890
 891 /*-----------------------------------------------------------------------
 892  * PSDMR - 60x Bus SDRAM Mode Register
 893  *     Ref: Section 10.3.3 on page 10-21
 894  *-----------------------------------------------------------------------
 895  */
 896
 897 /* Address that the DIMM SPD memory lives at.
 898  */
 899 #define SDRAM_SPD_ADDR 0x50
 900
 901 #if (CFG_SDRAM0_SIZE == 64)
 902 /* With a 64 MB DIMM, the PSDMR is configured as follows:
 903  *
 904  *     - Bank Based Interleaving,
 905  *     - Refresh Enable,
 906  *     - Address Multiplexing where A5 is output on A14 pin
 907  *       (A6 on A15, and so on),
 908  *     - use address pins A14-A16 as bank select,
 909  *     - A9 is output on SDA10 during an ACTIVATE command,
 910  *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
 911  *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 912  *       is 3 clocks,
 913  *     - earliest timing for READ/WRITE command after ACTIVATE command is
 914  *       2 clocks,
 915  *     - earliest timing for PRECHARGE after last data was read is 1 clock,
 916  *     - earliest timing for PRECHARGE after last data was written is 1 clock,
 917  *     - CAS Latency is 2.
 918  */
 919 #define CFG_PSDMR       (PSDMR_RFEN           |\
 920                          PSDMR_SDAM_A14_IS_A5 |\
 921                          PSDMR_BSMA_A14_A16   |\
 922                          PSDMR_SDA10_PBI0_A9  |\
 923                          PSDMR_RFRC_7_CLK     |\
 924                          PSDMR_PRETOACT_3W    |\
 925                          PSDMR_ACTTORW_2W     |\
 926                          PSDMR_LDOTOPRE_1C    |\
 927                          PSDMR_WRC_1C         |\
 928                          PSDMR_CL_2)
 929 #else
 930 #error "INVALID SDRAM CONFIGURATION"
 931 #endif
 932
 933 /*
 934  * Shoot for approximately 1MHz on the prescaler.
 935  */
 936 #if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
 937 #define CFG_MPTPR       MPTPR_PTP_DIV64
 938 #elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
 939 #define CFG_MPTPR       MPTPR_PTP_DIV32
 940 #else
 941 #warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
 942 #define CFG_MPTPR       MPTPR_PTP_DIV32
 943 #endif
 944 #define CFG_PSRT        14
 945
 946
 947 /*-----------------------------------------------------------------------
 948  * BR6 - Base Register
 949  *     Ref: Section 10.3.1 on page 10-14
 950  * OR6 - Option Register
 951  *     Ref: Section 10.3.2 on page 10-18
 952  *-----------------------------------------------------------------------
 953  */
 954
 955 /* Bank 6 - Secondary FLASH
 956  *
 957  * The secondary FLASH is connected to *CS6
 958  */
 959 #if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
 960
 961 /* BR6 is configured as follows:
 962  *
 963  *     - Base address of 0x60000000
 964  *     - 16 bit port size
 965  *     - Data errors checking is disabled
 966  *     - Read and write access
 967  *     - GPCM 60x bus
 968  *     - Access are handled by the memory controller according to MSEL
 969  *     - Not used for atomic operations
 970  *     - No data pipelining is done
 971  *     - Valid
 972  */
 973 #  define CFG_BR6_PRELIM  ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
 974                            BRx_PS_16                      |\
 975                            BRx_MS_GPCM_P                  |\
 976                            BRx_V)
 977
 978 /* OR6 is configured as follows:
 979  *
 980  *     - 2 MB
 981  *     - *BCTL0 is asserted upon access to the current memory bank
 982  *     - *CW / *WE are negated a quarter of a clock earlier
 983  *     - *CS is output at the same time as the address lines
 984  *     - Uses a clock cycle length of 5
 985  *     - *PSDVAL is generated internally by the memory controller
 986  *       unless *GTA is asserted earlier externally.
 987  *     - Relaxed timing is generated by the GPCM for accesses
 988  *       initiated to this memory region.
 989  *     - One idle clock is inserted between a read access from the
 990  *       current bank and the next access.
 991  */
 992 #  define CFG_OR6_PRELIM  (MEG_TO_AM(CFG_FLASH1_SIZE)  |\
 993                            ORxG_CSNT                   |\
 994                            ORxG_ACS_DIV1               |\
 995                            ORxG_SCY_5_CLK              |\
 996                            ORxG_TRLX                   |\
 997                            ORxG_EHTR)
 998 #endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
 999
1000 /*
1001  * Internal Definitions
1002  *
1003  * Boot Flags
1004  */
1005 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
1006 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
1007
1008 #endif  /* __CONFIG_H */