include/configs/sama5d3xek.h

   1 /*
   2  * Configuation settings for the SAMA5D3xEK board.
   3  *
   4  * Copyright (C) 2012 - 2013 Atmel
   5  *
   6  * based on at91sam9m10g45ek.h by:
   7  * Stelian Pop <stelian@popies.net>
   8  * Lead Tech Design <www.leadtechdesign.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 #include "at91-sama5_common.h"
  17
  18 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  19
  20 /*
  21  * This needs to be defined for the OHCI code to work but it is defined as
  22  * ATMEL_ID_UHPHS in the CPU specific header files.
  23  */
  24 #define ATMEL_ID_UHP                    32
  25
  26 /*
  27  * Specify the clock enable bit in the PMC_SCER register.
  28  */
  29 #define ATMEL_PMC_UHP                   (1 <<  6)
  30
  31 /* board specific (not enough SRAM) */
  32 #define CONFIG_SAMA5D3_LCD_BASE         0x23E00000
  33
  34 /* NOR flash */
  35 #ifdef CONFIG_MTD_NOR_FLASH
  36 #define CONFIG_FLASH_CFI_DRIVER
  37 #define CONFIG_SYS_FLASH_CFI
  38 #define CONFIG_SYS_FLASH_PROTECTION
  39 #define CONFIG_SYS_FLASH_BASE           0x10000000
  40 #define CONFIG_SYS_MAX_FLASH_SECT       131
  41 #define CONFIG_SYS_MAX_FLASH_BANKS      1
  42 #endif
  43
  44 /* SDRAM */
  45 #define CONFIG_NR_DRAM_BANKS            1
  46 #define CONFIG_SYS_SDRAM_BASE           0x20000000
  47 #define CONFIG_SYS_SDRAM_SIZE           0x20000000
  48
  49 #ifdef CONFIG_SPL_BUILD
  50 #define CONFIG_SYS_INIT_SP_ADDR         0x318000
  51 #else
  52 #define CONFIG_SYS_INIT_SP_ADDR \
  53         (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  54 #endif
  55
  56 /* SerialFlash */
  57
  58 #ifdef CONFIG_CMD_SF
  59 #define CONFIG_SF_DEFAULT_SPEED         30000000
  60 #endif
  61
  62 /* NAND flash */
  63 #ifdef CONFIG_CMD_NAND
  64 #define CONFIG_NAND_ATMEL
  65 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  66 #define CONFIG_SYS_NAND_BASE            0x60000000
  67 /* our ALE is AD21 */
  68 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  69 /* our CLE is AD22 */
  70 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  71 #define CONFIG_SYS_NAND_ONFI_DETECTION
  72 #endif
  73 /* PMECC & PMERRLOC */
  74 #define CONFIG_ATMEL_NAND_HWECC
  75 #define CONFIG_ATMEL_NAND_HW_PMECC
  76 #define CONFIG_PMECC_CAP                4
  77 #define CONFIG_PMECC_SECTOR_SIZE        512
  78
  79 /* USB */
  80
  81 #ifdef CONFIG_CMD_USB
  82 #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
  83 #define CONFIG_USB_OHCI_NEW
  84 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  85 #define CONFIG_SYS_USB_OHCI_REGS_BASE           ATMEL_BASE_OHCI
  86 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "sama5d3"
  87 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      3
  88 #endif
  89
  90 #define CONFIG_SYS_LOAD_ADDR                    0x22000000 /* load address */
  91
  92 /* SPL */
  93 #define CONFIG_SPL_TEXT_BASE            0x300000
  94 #define CONFIG_SPL_MAX_SIZE             0x18000
  95 #define CONFIG_SPL_BSS_START_ADDR       0x20000000
  96 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  97 #define CONFIG_SYS_SPL_MALLOC_START     0x20080000
  98 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x80000
  99
 100 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)
 101
 102 #ifdef CONFIG_SD_BOOT
 103 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 104 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 105
 106 #elif CONFIG_SPI_BOOT
 107 #define CONFIG_SPL_SPI_LOAD
 108 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x10000
 109
 110 #elif CONFIG_NAND_BOOT
 111 #define CONFIG_SPL_NAND_DRIVERS
 112 #define CONFIG_SPL_NAND_BASE
 113 #endif
 114 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 115 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 116 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 117 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 118 #define CONFIG_SYS_NAND_OOBSIZE         64
 119 #define CONFIG_SYS_NAND_BLOCK_SIZE      0x20000
 120 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
 121 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
 122
 123 #endif