include/configs/sbc8349.h

   1 /*
   2  * WindRiver SBC8349 U-Boot configuration file.
   3  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   4  *
   5  * Paul Gortmaker <paul.gortmaker@windriver.com>
   6  * Based on the MPC8349EMDS config.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * sbc8349 board configuration file.
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * Top level Makefile configuration choices
  36  */
  37 #ifdef CONFIG_66
  38 #define PCI_66M
  39 #endif
  40
  41 #ifdef CONFIG_33
  42 #define PCI_33M
  43 #endif
  44
  45 /*
  46  * High Level Configuration Options
  47  */
  48 #define CONFIG_E300             1       /* E300 Family */
  49 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  50 #define CONFIG_MPC834x          1       /* MPC834x family */
  51 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  52 #define CONFIG_SBC8349          1       /* WRS SBC8349 board specific */
  53
  54 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  55 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  56
  57 /*
  58  * The default if PCI isn't enabled, or if no PCI clk setting is given
  59  * is 66MHz; this is what the board defaults to when the PCI slot is
  60  * physically empty.  The board will automatically (i.e w/o jumpers)
  61  * clock down to 33MHz if you insert a 33MHz PCI card.
  62  */
  63 #ifdef PCI_33M
  64 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  65 #else   /* 66M */
  66 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  67 #endif
  68
  69 #ifndef CONFIG_SYS_CLK_FREQ
  70 #ifdef PCI_33M
  71 #define CONFIG_SYS_CLK_FREQ     33000000
  72 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  73 #else   /* 66M */
  74 #define CONFIG_SYS_CLK_FREQ     66000000
  75 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  76 #endif
  77 #endif
  78
  79 #undef CONFIG_BOARD_EARLY_INIT_F                /* call board_pre_init */
  80
  81 #define CONFIG_SYS_IMMR         0xE0000000
  82
  83 #undef CONFIG_SYS_DRAM_TEST                             /* memory test, takes time */
  84 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  85 #define CONFIG_SYS_MEMTEST_END          0x00100000
  86
  87 /*
  88  * DDR Setup
  89  */
  90 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  91 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  92 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  93 #define CONFIG_SYS_83XX_DDR_USES_CS0            /* WRS; Fsl board uses CS2/CS3 */
  94
  95 /*
  96  * 32-bit data path mode.
  97  *
  98  * Please note that using this mode for devices with the real density of 64-bit
  99  * effectively reduces the amount of available memory due to the effect of
 100  * wrapping around while translating address to row/columns, for example in the
 101  * 256MB module the upper 128MB get aliased with contents of the lower
 102  * 128MB); normally this define should be used for devices with real 32-bit
 103  * data path.
 104  */
 105 #undef CONFIG_DDR_32BIT
 106
 107 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
 108 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 109 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 110 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
 111                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 112 #define CONFIG_DDR_2T_TIMING
 113
 114 #if defined(CONFIG_SPD_EEPROM)
 115 /*
 116  * Determine DDR configuration from I2C interface.
 117  */
 118 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
 119
 120 #else
 121 /*
 122  * Manually set up DDR parameters
 123  * NB: manual DDR setup untested on sbc834x
 124  */
 125 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 126 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 127 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 128 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 129 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 130 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 131
 132 #if defined(CONFIG_DDR_32BIT)
 133 /* set burst length to 8 for 32-bit data path */
 134 #define CONFIG_SYS_DDR_MODE             0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
 135 #else
 136 /* the default burst length is 4 - for 64-bit data path */
 137 #define CONFIG_SYS_DDR_MODE             0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
 138 #endif
 139 #endif
 140
 141 /*
 142  * SDRAM on the Local Bus
 143  */
 144 #define CONFIG_SYS_LBC_SDRAM_BASE       0x10000000      /* Localbus SDRAM */
 145 #define CONFIG_SYS_LBC_SDRAM_SIZE       128             /* LBC SDRAM is 128MB */
 146
 147 /*
 148  * FLASH on the Local Bus
 149  */
 150 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 151 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 152 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 153 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 154 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 155
 156 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
 157                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */   \
 158                                 BR_V)                   /* valid */
 159
 160 #define CONFIG_SYS_OR0_PRELIM           0xFF806FF7      /* 8 MB flash size */
 161 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* window base at flash base */
 162 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 163
 164 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 165 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 166
 167 #undef CONFIG_SYS_FLASH_CHECKSUM
 168 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 169 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 170
 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 172
 173 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 174 #define CONFIG_SYS_RAMBOOT
 175 #else
 176 #undef  CONFIG_SYS_RAMBOOT
 177 #endif
 178
 179 #define CONFIG_SYS_INIT_RAM_LOCK        1
 180 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000              /* Initial RAM address */
 181 #define CONFIG_SYS_INIT_RAM_END 0x1000                  /* End of used area in RAM*/
 182
 183 #define CONFIG_SYS_GBL_DATA_SIZE        0x100                   /* num bytes initial data */
 184 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 185 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 186
 187 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)            /* Reserve 256 kB for Mon */
 188 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)            /* Reserved for malloc */
 189
 190 /*
 191  * Local Bus LCRR and LBCR regs
 192  *    LCRR:  DLL bypass, Clock divider is 4
 193  * External Local Bus rate is
 194  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 195  */
 196 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 197 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 198 #define CONFIG_SYS_LBC_LBCR     0x00000000
 199
 200 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 201
 202 #ifdef CONFIG_SYS_LB_SDRAM
 203 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 204 /*
 205  * Base Register 2 and Option Register 2 configure SDRAM.
 206  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 207  *
 208  * For BR2, need:
 209  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 210  *    port-size = 32-bits = BR2[19:20] = 11
 211  *    no parity checking = BR2[21:22] = 00
 212  *    SDRAM for MSEL = BR2[24:26] = 011
 213  *    Valid = BR[31] = 1
 214  *
 215  * 0    4    8    12   16   20   24   28
 216  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 217  *
 218  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 219  * FIXME: the top 17 bits of BR2.
 220  */
 221
 222 #define CONFIG_SYS_BR2_PRELIM           0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 223 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0xF0000000
 224 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* 64M */
 225
 226 /*
 227  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 228  *
 229  * For OR2, need:
 230  *    64MB mask for AM, OR2[0:7] = 1111 1100
 231  *                 XAM, OR2[17:18] = 11
 232  *    9 columns OR2[19-21] = 010
 233  *    13 rows   OR2[23-25] = 100
 234  *    EAD set for extra time OR[31] = 1
 235  *
 236  * 0    4    8    12   16   20   24   28
 237  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 238  */
 239
 240 #define CONFIG_SYS_OR2_PRELIM   0xFC006901
 241
 242 #define CONFIG_SYS_LBC_LSRT     0x32000000    /* LB sdram refresh timer, about 6us */
 243 #define CONFIG_SYS_LBC_MRTPR    0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 244
 245 #define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
 246                                 | LSDMR_BSMA1516        \
 247                                 | LSDMR_RFCR8           \
 248                                 | LSDMR_PRETOACT6       \
 249                                 | LSDMR_ACTTORW3        \
 250                                 | LSDMR_BL8             \
 251                                 | LSDMR_WRC3            \
 252                                 | LSDMR_CL3             \
 253                                 )
 254
 255 /*
 256  * SDRAM Controller configuration sequence.
 257  */
 258 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 259 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 260 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 261 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 262 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 263 #endif
 264
 265 /*
 266  * Serial Port
 267  */
 268 #define CONFIG_CONS_INDEX     1
 269 #define CONFIG_SYS_NS16550
 270 #define CONFIG_SYS_NS16550_SERIAL
 271 #define CONFIG_SYS_NS16550_REG_SIZE    1
 272 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 273
 274 #define CONFIG_SYS_BAUDRATE_TABLE  \
 275         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 276
 277 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 278 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 279
 280 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 281 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 282 /* Use the HUSH parser */
 283 #define CONFIG_SYS_HUSH_PARSER
 284 #ifdef  CONFIG_SYS_HUSH_PARSER
 285 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 286 #endif
 287
 288 /* pass open firmware flat tree */
 289 #define CONFIG_OF_LIBFDT        1
 290 #define CONFIG_OF_BOARD_SETUP   1
 291 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 292
 293 /* I2C */
 294 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 295 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 296 #define CONFIG_FSL_I2C
 297 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 298 #define CONFIG_SYS_I2C_SLAVE            0x7F
 299 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 300 #define CONFIG_SYS_I2C1_OFFSET          0x3000
 301 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 302 #define CONFIG_SYS_I2C_OFFSET           CONFIG_SYS_I2C2_OFFSET
 303 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 304
 305 /* TSEC */
 306 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 307 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 308 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 309 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 310
 311 /*
 312  * General PCI
 313  * Addresses are mapped 1-1.
 314  */
 315 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 316 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 317 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 318 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 319 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 320 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 321 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 322 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 323 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 324
 325 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 326 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 327 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 328 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 329 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 330 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 331 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 332 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
 333 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 334
 335 #if defined(CONFIG_PCI)
 336
 337 #define PCI_64BIT
 338 #define PCI_ONE_PCI1
 339 #if defined(PCI_64BIT)
 340 #undef PCI_ALL_PCI1
 341 #undef PCI_TWO_PCI1
 342 #undef PCI_ONE_PCI1
 343 #endif
 344
 345 #define CONFIG_NET_MULTI
 346 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 347
 348 #undef CONFIG_EEPRO100
 349 #undef CONFIG_TULIP
 350
 351 #if !defined(CONFIG_PCI_PNP)
 352         #define PCI_ENET0_IOADDR        0xFIXME
 353         #define PCI_ENET0_MEMADDR       0xFIXME
 354         #define PCI_IDSEL_NUMBER        0xFIXME
 355 #endif
 356
 357 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 358 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 359
 360 #endif  /* CONFIG_PCI */
 361
 362 /*
 363  * TSEC configuration
 364  */
 365 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 366
 367 #if defined(CONFIG_TSEC_ENET)
 368 #ifndef CONFIG_NET_MULTI
 369 #define CONFIG_NET_MULTI        1
 370 #endif
 371
 372 #define CONFIG_TSEC1    1
 373 #define CONFIG_TSEC1_NAME       "TSEC0"
 374 #define CONFIG_TSEC2    1
 375 #define CONFIG_TSEC2_NAME       "TSEC1"
 376 #define CONFIG_PHY_BCM5421S     1
 377 #define TSEC1_PHY_ADDR          0x19
 378 #define TSEC2_PHY_ADDR          0x1a
 379 #define TSEC1_PHYIDX            0
 380 #define TSEC2_PHYIDX            0
 381 #define TSEC1_FLAGS             TSEC_GIGABIT
 382 #define TSEC2_FLAGS             TSEC_GIGABIT
 383
 384 /* Options are: TSEC[0-1] */
 385 #define CONFIG_ETHPRIME         "TSEC0"
 386
 387 #endif  /* CONFIG_TSEC_ENET */
 388
 389 /*
 390  * Environment
 391  */
 392 #ifndef CONFIG_SYS_RAMBOOT
 393         #define CONFIG_ENV_IS_IN_FLASH  1
 394         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 395         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 396         #define CONFIG_ENV_SIZE         0x2000
 397
 398 /* Address and size of Redundant Environment Sector     */
 399 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 400 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 401
 402 #else
 403         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 404         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 405         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 406         #define CONFIG_ENV_SIZE         0x2000
 407 #endif
 408
 409 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 410 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 411
 412
 413 /*
 414  * BOOTP options
 415  */
 416 #define CONFIG_BOOTP_BOOTFILESIZE
 417 #define CONFIG_BOOTP_BOOTPATH
 418 #define CONFIG_BOOTP_GATEWAY
 419 #define CONFIG_BOOTP_HOSTNAME
 420
 421
 422 /*
 423  * Command line configuration.
 424  */
 425 #include <config_cmd_default.h>
 426
 427 #define CONFIG_CMD_I2C
 428 #define CONFIG_CMD_MII
 429 #define CONFIG_CMD_PING
 430
 431 #if defined(CONFIG_PCI)
 432     #define CONFIG_CMD_PCI
 433 #endif
 434
 435 #if defined(CONFIG_SYS_RAMBOOT)
 436     #undef CONFIG_CMD_SAVEENV
 437     #undef CONFIG_CMD_LOADS
 438 #endif
 439
 440
 441 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 442
 443 /*
 444  * Miscellaneous configurable options
 445  */
 446 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 447 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 448 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 449
 450 #if defined(CONFIG_CMD_KGDB)
 451         #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 452 #else
 453         #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 454 #endif
 455
 456 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 457 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 458 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 459 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 460
 461 /*
 462  * For booting Linux, the board info and command line data
 463  * have to be in the first 256 MB of memory, since this is
 464  * the maximum mapped by the Linux kernel during initialization.
 465  */
 466 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 467
 468 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 469
 470 #if 1 /*528/264*/
 471 #define CONFIG_SYS_HRCW_LOW (\
 472         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 473         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 474         HRCWL_CSB_TO_CLKIN |\
 475         HRCWL_VCO_1X2 |\
 476         HRCWL_CORE_TO_CSB_2X1)
 477 #elif 0 /*396/132*/
 478 #define CONFIG_SYS_HRCW_LOW (\
 479         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 480         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 481         HRCWL_CSB_TO_CLKIN |\
 482         HRCWL_VCO_1X4 |\
 483         HRCWL_CORE_TO_CSB_3X1)
 484 #elif 0 /*264/132*/
 485 #define CONFIG_SYS_HRCW_LOW (\
 486         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 487         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 488         HRCWL_CSB_TO_CLKIN |\
 489         HRCWL_VCO_1X4 |\
 490         HRCWL_CORE_TO_CSB_2X1)
 491 #elif 0 /*132/132*/
 492 #define CONFIG_SYS_HRCW_LOW (\
 493         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 494         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 495         HRCWL_CSB_TO_CLKIN |\
 496         HRCWL_VCO_1X4 |\
 497         HRCWL_CORE_TO_CSB_1X1)
 498 #elif 0 /*264/264 */
 499 #define CONFIG_SYS_HRCW_LOW (\
 500         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 501         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 502         HRCWL_CSB_TO_CLKIN |\
 503         HRCWL_VCO_1X4 |\
 504         HRCWL_CORE_TO_CSB_1X1)
 505 #endif
 506
 507 #if defined(PCI_64BIT)
 508 #define CONFIG_SYS_HRCW_HIGH (\
 509         HRCWH_PCI_HOST |\
 510         HRCWH_64_BIT_PCI |\
 511         HRCWH_PCI1_ARBITER_ENABLE |\
 512         HRCWH_PCI2_ARBITER_DISABLE |\
 513         HRCWH_CORE_ENABLE |\
 514         HRCWH_FROM_0X00000100 |\
 515         HRCWH_BOOTSEQ_DISABLE |\
 516         HRCWH_SW_WATCHDOG_DISABLE |\
 517         HRCWH_ROM_LOC_LOCAL_16BIT |\
 518         HRCWH_TSEC1M_IN_GMII |\
 519         HRCWH_TSEC2M_IN_GMII )
 520 #else
 521 #define CONFIG_SYS_HRCW_HIGH (\
 522         HRCWH_PCI_HOST |\
 523         HRCWH_32_BIT_PCI |\
 524         HRCWH_PCI1_ARBITER_ENABLE |\
 525         HRCWH_PCI2_ARBITER_ENABLE |\
 526         HRCWH_CORE_ENABLE |\
 527         HRCWH_FROM_0X00000100 |\
 528         HRCWH_BOOTSEQ_DISABLE |\
 529         HRCWH_SW_WATCHDOG_DISABLE |\
 530         HRCWH_ROM_LOC_LOCAL_16BIT |\
 531         HRCWH_TSEC1M_IN_GMII |\
 532         HRCWH_TSEC2M_IN_GMII )
 533 #endif
 534
 535 /* System IO Config */
 536 #define CONFIG_SYS_SICRH 0
 537 #define CONFIG_SYS_SICRL SICRL_LDP_A
 538
 539 #define CONFIG_SYS_HID0_INIT    0x000000000
 540 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 541                                  HID0_ENABLE_INSTRUCTION_CACHE)
 542
 543 /* #define CONFIG_SYS_HID0_FINAL                (\
 544         HID0_ENABLE_INSTRUCTION_CACHE |\
 545         HID0_ENABLE_M_BIT |\
 546         HID0_ENABLE_ADDRESS_BROADCAST ) */
 547
 548
 549 #define CONFIG_SYS_HID2 HID2_HBE
 550
 551 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 552
 553 /* DDR @ 0x00000000 */
 554 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 555 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 556
 557 /* PCI @ 0x80000000 */
 558 #ifdef CONFIG_PCI
 559 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 560 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 561 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 562 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 563 #else
 564 #define CONFIG_SYS_IBAT1L       (0)
 565 #define CONFIG_SYS_IBAT1U       (0)
 566 #define CONFIG_SYS_IBAT2L       (0)
 567 #define CONFIG_SYS_IBAT2U       (0)
 568 #endif
 569
 570 #ifdef CONFIG_MPC83XX_PCI2
 571 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 572 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 573 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 574 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 575 #else
 576 #define CONFIG_SYS_IBAT3L       (0)
 577 #define CONFIG_SYS_IBAT3U       (0)
 578 #define CONFIG_SYS_IBAT4L       (0)
 579 #define CONFIG_SYS_IBAT4U       (0)
 580 #endif
 581
 582 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 583 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 584 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 585
 586 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 587 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 588                                  BATL_GUARDEDSTORAGE)
 589 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 590
 591 #define CONFIG_SYS_IBAT7L       (0)
 592 #define CONFIG_SYS_IBAT7U       (0)
 593
 594 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 595 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 596 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 597 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 598 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 599 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 600 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 601 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 602 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 603 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 604 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 605 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 606 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 607 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 608 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 609 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 610
 611 /*
 612  * Internal Definitions
 613  *
 614  * Boot Flags
 615  */
 616 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 617 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 618
 619 #if defined(CONFIG_CMD_KGDB)
 620 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 621 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 622 #endif
 623
 624 /*
 625  * Environment Configuration
 626  */
 627 #define CONFIG_ENV_OVERWRITE
 628
 629 #if defined(CONFIG_TSEC_ENET)
 630 #define CONFIG_HAS_ETH0
 631 #define CONFIG_HAS_ETH1
 632 #endif
 633
 634 #define CONFIG_HOSTNAME         SBC8349
 635 #define CONFIG_ROOTPATH         /tftpboot/rootfs
 636 #define CONFIG_BOOTFILE         uImage
 637
 638 #define CONFIG_LOADADDR         800000  /* default location for tftp and bootm */
 639
 640 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 641 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 642
 643 #define CONFIG_BAUDRATE  115200
 644
 645 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 646         "netdev=eth0\0"                                                 \
 647         "hostname=sbc8349\0"                                            \
 648         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 649                 "nfsroot=${serverip}:${rootpath}\0"                     \
 650         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 651         "addip=setenv bootargs ${bootargs} "                            \
 652                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 653                 ":${hostname}:${netdev}:off panic=1\0"                  \
 654         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 655         "flash_nfs=run nfsargs addip addtty;"                           \
 656                 "bootm ${kernel_addr}\0"                                \
 657         "flash_self=run ramargs addip addtty;"                          \
 658                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 659         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 660                 "bootm\0"                                               \
 661         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 662         "update=protect off ff800000 ff83ffff; "                        \
 663                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0"     \
 664         "upd=run load update\0"                                         \
 665         "fdtaddr=780000\0"                                              \
 666         "fdtfile=sbc8349.dtb\0"                                         \
 667         ""
 668
 669 #define CONFIG_NFSBOOTCOMMAND                                           \
 670    "setenv bootargs root=/dev/nfs rw "                                  \
 671       "nfsroot=$serverip:$rootpath "                                    \
 672       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 673       "console=$consoledev,$baudrate $othbootargs;"                     \
 674    "tftp $loadaddr $bootfile;"                                          \
 675    "tftp $fdtaddr $fdtfile;"                                            \
 676    "bootm $loadaddr - $fdtaddr"
 677
 678 #define CONFIG_RAMBOOTCOMMAND                                           \
 679    "setenv bootargs root=/dev/ram rw "                                  \
 680       "console=$consoledev,$baudrate $othbootargs;"                     \
 681    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 682    "tftp $loadaddr $bootfile;"                                          \
 683    "tftp $fdtaddr $fdtfile;"                                            \
 684    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 685
 686 #define CONFIG_BOOTCOMMAND      "run flash_self"
 687
 688 #endif  /* __CONFIG_H */