include/configs/sbc8349.h

   1 /*
   2  * WindRiver SBC8349 U-Boot configuration file.
   3  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   4  *
   5  * Paul Gortmaker <paul.gortmaker@windriver.com>
   6  * Based on the MPC8349EMDS config.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * sbc8349 board configuration file.
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  */
  37 #define CONFIG_E300             1       /* E300 Family */
  38 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  39 #define CONFIG_MPC834x          1       /* MPC834x family */
  40 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  41 #define CONFIG_SBC8349          1       /* WRS SBC8349 board specific */
  42
  43 #define CONFIG_SYS_TEXT_BASE    0xFF800000
  44
  45 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  46 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  47
  48 /*
  49  * The default if PCI isn't enabled, or if no PCI clk setting is given
  50  * is 66MHz; this is what the board defaults to when the PCI slot is
  51  * physically empty.  The board will automatically (i.e w/o jumpers)
  52  * clock down to 33MHz if you insert a 33MHz PCI card.
  53  */
  54 #ifdef CONFIG_PCI_33M
  55 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  56 #else   /* 66M */
  57 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  58 #endif
  59
  60 #ifndef CONFIG_SYS_CLK_FREQ
  61 #ifdef CONFIG_PCI_33M
  62 #define CONFIG_SYS_CLK_FREQ     33000000
  63 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  64 #else   /* 66M */
  65 #define CONFIG_SYS_CLK_FREQ     66000000
  66 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  67 #endif
  68 #endif
  69
  70 #undef CONFIG_BOARD_EARLY_INIT_F                /* call board_pre_init */
  71
  72 #define CONFIG_SYS_IMMR         0xE0000000
  73
  74 #undef CONFIG_SYS_DRAM_TEST                             /* memory test, takes time */
  75 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  76 #define CONFIG_SYS_MEMTEST_END          0x00100000
  77
  78 /*
  79  * DDR Setup
  80  */
  81 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  82 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  83 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  84 #define CONFIG_SYS_83XX_DDR_USES_CS0            /* WRS; Fsl board uses CS2/CS3 */
  85
  86 /*
  87  * 32-bit data path mode.
  88  *
  89  * Please note that using this mode for devices with the real density of 64-bit
  90  * effectively reduces the amount of available memory due to the effect of
  91  * wrapping around while translating address to row/columns, for example in the
  92  * 256MB module the upper 128MB get aliased with contents of the lower
  93  * 128MB); normally this define should be used for devices with real 32-bit
  94  * data path.
  95  */
  96 #undef CONFIG_DDR_32BIT
  97
  98 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  99 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
 100 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
 101 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
 102                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
 103 #define CONFIG_DDR_2T_TIMING
 104
 105 #if defined(CONFIG_SPD_EEPROM)
 106 /*
 107  * Determine DDR configuration from I2C interface.
 108  */
 109 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
 110
 111 #else
 112 /*
 113  * Manually set up DDR parameters
 114  * NB: manual DDR setup untested on sbc834x
 115  */
 116 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 117 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 118 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 119 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 120 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 121 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 122
 123 #if defined(CONFIG_DDR_32BIT)
 124 /* set burst length to 8 for 32-bit data path */
 125 #define CONFIG_SYS_DDR_MODE             0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
 126 #else
 127 /* the default burst length is 4 - for 64-bit data path */
 128 #define CONFIG_SYS_DDR_MODE             0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
 129 #endif
 130 #endif
 131
 132 /*
 133  * SDRAM on the Local Bus
 134  */
 135 #define CONFIG_SYS_LBC_SDRAM_BASE       0x10000000      /* Localbus SDRAM */
 136 #define CONFIG_SYS_LBC_SDRAM_SIZE       128             /* LBC SDRAM is 128MB */
 137
 138 /*
 139  * FLASH on the Local Bus
 140  */
 141 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 142 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 143 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 144 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 145 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 146
 147 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
 148                                 (2 << BR_PS_SHIFT) |    /* 16 bit port size */   \
 149                                 BR_V)                   /* valid */
 150
 151 #define CONFIG_SYS_OR0_PRELIM           0xFF806FF7      /* 8 MB flash size */
 152 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* window base at flash base */
 153 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 154
 155 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 156 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 157
 158 #undef CONFIG_SYS_FLASH_CHECKSUM
 159 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 160 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 161
 162 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 163
 164 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 165 #define CONFIG_SYS_RAMBOOT
 166 #else
 167 #undef  CONFIG_SYS_RAMBOOT
 168 #endif
 169
 170 #define CONFIG_SYS_INIT_RAM_LOCK        1
 171 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000              /* Initial RAM address */
 172 #define CONFIG_SYS_INIT_RAM_END 0x1000                  /* End of used area in RAM*/
 173
 174 #define CONFIG_SYS_GBL_DATA_SIZE        0x100                   /* num bytes initial data */
 175 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 176 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 177
 178 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)            /* Reserve 256 kB for Mon */
 179 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)            /* Reserved for malloc */
 180
 181 /*
 182  * Local Bus LCRR and LBCR regs
 183  *    LCRR:  DLL bypass, Clock divider is 4
 184  * External Local Bus rate is
 185  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 186  */
 187 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 188 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 189 #define CONFIG_SYS_LBC_LBCR     0x00000000
 190
 191 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 192
 193 #ifdef CONFIG_SYS_LB_SDRAM
 194 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 195 /*
 196  * Base Register 2 and Option Register 2 configure SDRAM.
 197  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 198  *
 199  * For BR2, need:
 200  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 201  *    port-size = 32-bits = BR2[19:20] = 11
 202  *    no parity checking = BR2[21:22] = 00
 203  *    SDRAM for MSEL = BR2[24:26] = 011
 204  *    Valid = BR[31] = 1
 205  *
 206  * 0    4    8    12   16   20   24   28
 207  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 208  *
 209  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 210  * FIXME: the top 17 bits of BR2.
 211  */
 212
 213 #define CONFIG_SYS_BR2_PRELIM           0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 214 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0xF0000000
 215 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* 64M */
 216
 217 /*
 218  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 219  *
 220  * For OR2, need:
 221  *    64MB mask for AM, OR2[0:7] = 1111 1100
 222  *                 XAM, OR2[17:18] = 11
 223  *    9 columns OR2[19-21] = 010
 224  *    13 rows   OR2[23-25] = 100
 225  *    EAD set for extra time OR[31] = 1
 226  *
 227  * 0    4    8    12   16   20   24   28
 228  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 229  */
 230
 231 #define CONFIG_SYS_OR2_PRELIM   0xFC006901
 232
 233 #define CONFIG_SYS_LBC_LSRT     0x32000000    /* LB sdram refresh timer, about 6us */
 234 #define CONFIG_SYS_LBC_MRTPR    0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 235
 236 #define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
 237                                 | LSDMR_BSMA1516        \
 238                                 | LSDMR_RFCR8           \
 239                                 | LSDMR_PRETOACT6       \
 240                                 | LSDMR_ACTTORW3        \
 241                                 | LSDMR_BL8             \
 242                                 | LSDMR_WRC3            \
 243                                 | LSDMR_CL3             \
 244                                 )
 245
 246 /*
 247  * SDRAM Controller configuration sequence.
 248  */
 249 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 250 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 251 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 252 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 253 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 254 #endif
 255
 256 /*
 257  * Serial Port
 258  */
 259 #define CONFIG_CONS_INDEX     1
 260 #define CONFIG_SYS_NS16550
 261 #define CONFIG_SYS_NS16550_SERIAL
 262 #define CONFIG_SYS_NS16550_REG_SIZE    1
 263 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 264
 265 #define CONFIG_SYS_BAUDRATE_TABLE  \
 266         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 267
 268 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 269 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 270
 271 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 272 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support   */
 273 /* Use the HUSH parser */
 274 #define CONFIG_SYS_HUSH_PARSER
 275 #ifdef  CONFIG_SYS_HUSH_PARSER
 276 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 277 #endif
 278
 279 /* pass open firmware flat tree */
 280 #define CONFIG_OF_LIBFDT        1
 281 #define CONFIG_OF_BOARD_SETUP   1
 282 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 283
 284 /* I2C */
 285 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 286 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 287 #define CONFIG_FSL_I2C
 288 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 289 #define CONFIG_SYS_I2C_SLAVE            0x7F
 290 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 291 #define CONFIG_SYS_I2C1_OFFSET          0x3000
 292 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 293 #define CONFIG_SYS_I2C_OFFSET           CONFIG_SYS_I2C2_OFFSET
 294 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 295
 296 /* TSEC */
 297 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 298 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 299 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 300 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 301
 302 /*
 303  * General PCI
 304  * Addresses are mapped 1-1.
 305  */
 306 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 307 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 308 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 309 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 310 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 311 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 312 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 313 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 314 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 315
 316 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 317 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 318 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 319 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 320 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 321 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 322 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 323 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
 324 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 325
 326 #if defined(CONFIG_PCI)
 327
 328 #define PCI_64BIT
 329 #define PCI_ONE_PCI1
 330 #if defined(PCI_64BIT)
 331 #undef PCI_ALL_PCI1
 332 #undef PCI_TWO_PCI1
 333 #undef PCI_ONE_PCI1
 334 #endif
 335
 336 #define CONFIG_NET_MULTI
 337 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 338
 339 #undef CONFIG_EEPRO100
 340 #undef CONFIG_TULIP
 341
 342 #if !defined(CONFIG_PCI_PNP)
 343         #define PCI_ENET0_IOADDR        0xFIXME
 344         #define PCI_ENET0_MEMADDR       0xFIXME
 345         #define PCI_IDSEL_NUMBER        0xFIXME
 346 #endif
 347
 348 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 349 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 350
 351 #endif  /* CONFIG_PCI */
 352
 353 /*
 354  * TSEC configuration
 355  */
 356 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 357
 358 #if defined(CONFIG_TSEC_ENET)
 359 #ifndef CONFIG_NET_MULTI
 360 #define CONFIG_NET_MULTI        1
 361 #endif
 362
 363 #define CONFIG_TSEC1    1
 364 #define CONFIG_TSEC1_NAME       "TSEC0"
 365 #define CONFIG_TSEC2    1
 366 #define CONFIG_TSEC2_NAME       "TSEC1"
 367 #define CONFIG_PHY_BCM5421S     1
 368 #define TSEC1_PHY_ADDR          0x19
 369 #define TSEC2_PHY_ADDR          0x1a
 370 #define TSEC1_PHYIDX            0
 371 #define TSEC2_PHYIDX            0
 372 #define TSEC1_FLAGS             TSEC_GIGABIT
 373 #define TSEC2_FLAGS             TSEC_GIGABIT
 374
 375 /* Options are: TSEC[0-1] */
 376 #define CONFIG_ETHPRIME         "TSEC0"
 377
 378 #endif  /* CONFIG_TSEC_ENET */
 379
 380 /*
 381  * Environment
 382  */
 383 #ifndef CONFIG_SYS_RAMBOOT
 384         #define CONFIG_ENV_IS_IN_FLASH  1
 385         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 386         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 387         #define CONFIG_ENV_SIZE         0x2000
 388
 389 /* Address and size of Redundant Environment Sector     */
 390 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 391 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 392
 393 #else
 394         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 395         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 396         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 397         #define CONFIG_ENV_SIZE         0x2000
 398 #endif
 399
 400 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 401 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 402
 403
 404 /*
 405  * BOOTP options
 406  */
 407 #define CONFIG_BOOTP_BOOTFILESIZE
 408 #define CONFIG_BOOTP_BOOTPATH
 409 #define CONFIG_BOOTP_GATEWAY
 410 #define CONFIG_BOOTP_HOSTNAME
 411
 412
 413 /*
 414  * Command line configuration.
 415  */
 416 #include <config_cmd_default.h>
 417
 418 #define CONFIG_CMD_I2C
 419 #define CONFIG_CMD_MII
 420 #define CONFIG_CMD_PING
 421
 422 #if defined(CONFIG_PCI)
 423     #define CONFIG_CMD_PCI
 424 #endif
 425
 426 #if defined(CONFIG_SYS_RAMBOOT)
 427     #undef CONFIG_CMD_SAVEENV
 428     #undef CONFIG_CMD_LOADS
 429 #endif
 430
 431
 432 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 433
 434 /*
 435  * Miscellaneous configurable options
 436  */
 437 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 438 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 439 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 440
 441 #if defined(CONFIG_CMD_KGDB)
 442         #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 443 #else
 444         #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 445 #endif
 446
 447 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 448 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 449 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 450 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 451
 452 /*
 453  * For booting Linux, the board info and command line data
 454  * have to be in the first 256 MB of memory, since this is
 455  * the maximum mapped by the Linux kernel during initialization.
 456  */
 457 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Initial Memory map for Linux*/
 458
 459 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 460
 461 #if 1 /*528/264*/
 462 #define CONFIG_SYS_HRCW_LOW (\
 463         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 464         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 465         HRCWL_CSB_TO_CLKIN |\
 466         HRCWL_VCO_1X2 |\
 467         HRCWL_CORE_TO_CSB_2X1)
 468 #elif 0 /*396/132*/
 469 #define CONFIG_SYS_HRCW_LOW (\
 470         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 471         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 472         HRCWL_CSB_TO_CLKIN |\
 473         HRCWL_VCO_1X4 |\
 474         HRCWL_CORE_TO_CSB_3X1)
 475 #elif 0 /*264/132*/
 476 #define CONFIG_SYS_HRCW_LOW (\
 477         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 478         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 479         HRCWL_CSB_TO_CLKIN |\
 480         HRCWL_VCO_1X4 |\
 481         HRCWL_CORE_TO_CSB_2X1)
 482 #elif 0 /*132/132*/
 483 #define CONFIG_SYS_HRCW_LOW (\
 484         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 485         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 486         HRCWL_CSB_TO_CLKIN |\
 487         HRCWL_VCO_1X4 |\
 488         HRCWL_CORE_TO_CSB_1X1)
 489 #elif 0 /*264/264 */
 490 #define CONFIG_SYS_HRCW_LOW (\
 491         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 492         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 493         HRCWL_CSB_TO_CLKIN |\
 494         HRCWL_VCO_1X4 |\
 495         HRCWL_CORE_TO_CSB_1X1)
 496 #endif
 497
 498 #if defined(PCI_64BIT)
 499 #define CONFIG_SYS_HRCW_HIGH (\
 500         HRCWH_PCI_HOST |\
 501         HRCWH_64_BIT_PCI |\
 502         HRCWH_PCI1_ARBITER_ENABLE |\
 503         HRCWH_PCI2_ARBITER_DISABLE |\
 504         HRCWH_CORE_ENABLE |\
 505         HRCWH_FROM_0X00000100 |\
 506         HRCWH_BOOTSEQ_DISABLE |\
 507         HRCWH_SW_WATCHDOG_DISABLE |\
 508         HRCWH_ROM_LOC_LOCAL_16BIT |\
 509         HRCWH_TSEC1M_IN_GMII |\
 510         HRCWH_TSEC2M_IN_GMII )
 511 #else
 512 #define CONFIG_SYS_HRCW_HIGH (\
 513         HRCWH_PCI_HOST |\
 514         HRCWH_32_BIT_PCI |\
 515         HRCWH_PCI1_ARBITER_ENABLE |\
 516         HRCWH_PCI2_ARBITER_ENABLE |\
 517         HRCWH_CORE_ENABLE |\
 518         HRCWH_FROM_0X00000100 |\
 519         HRCWH_BOOTSEQ_DISABLE |\
 520         HRCWH_SW_WATCHDOG_DISABLE |\
 521         HRCWH_ROM_LOC_LOCAL_16BIT |\
 522         HRCWH_TSEC1M_IN_GMII |\
 523         HRCWH_TSEC2M_IN_GMII )
 524 #endif
 525
 526 /* System IO Config */
 527 #define CONFIG_SYS_SICRH 0
 528 #define CONFIG_SYS_SICRL SICRL_LDP_A
 529
 530 #define CONFIG_SYS_HID0_INIT    0x000000000
 531 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 532                                  HID0_ENABLE_INSTRUCTION_CACHE)
 533
 534 /* #define CONFIG_SYS_HID0_FINAL                (\
 535         HID0_ENABLE_INSTRUCTION_CACHE |\
 536         HID0_ENABLE_M_BIT |\
 537         HID0_ENABLE_ADDRESS_BROADCAST ) */
 538
 539
 540 #define CONFIG_SYS_HID2 HID2_HBE
 541
 542 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 543
 544 /* DDR @ 0x00000000 */
 545 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 546 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 547
 548 /* PCI @ 0x80000000 */
 549 #ifdef CONFIG_PCI
 550 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 551 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 552 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 553 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 554 #else
 555 #define CONFIG_SYS_IBAT1L       (0)
 556 #define CONFIG_SYS_IBAT1U       (0)
 557 #define CONFIG_SYS_IBAT2L       (0)
 558 #define CONFIG_SYS_IBAT2U       (0)
 559 #endif
 560
 561 #ifdef CONFIG_MPC83XX_PCI2
 562 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 563 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 564 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 565 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 566 #else
 567 #define CONFIG_SYS_IBAT3L       (0)
 568 #define CONFIG_SYS_IBAT3U       (0)
 569 #define CONFIG_SYS_IBAT4L       (0)
 570 #define CONFIG_SYS_IBAT4U       (0)
 571 #endif
 572
 573 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 574 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 575 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 576
 577 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 578 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 579                                  BATL_GUARDEDSTORAGE)
 580 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 581
 582 #define CONFIG_SYS_IBAT7L       (0)
 583 #define CONFIG_SYS_IBAT7U       (0)
 584
 585 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 586 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 587 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 588 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 589 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 590 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 591 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 592 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 593 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 594 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 595 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 596 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 597 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 598 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 599 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 600 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 601
 602 #if defined(CONFIG_CMD_KGDB)
 603 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 604 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 605 #endif
 606
 607 /*
 608  * Environment Configuration
 609  */
 610 #define CONFIG_ENV_OVERWRITE
 611
 612 #if defined(CONFIG_TSEC_ENET)
 613 #define CONFIG_HAS_ETH0
 614 #define CONFIG_HAS_ETH1
 615 #endif
 616
 617 #define CONFIG_HOSTNAME         SBC8349
 618 #define CONFIG_ROOTPATH         /tftpboot/rootfs
 619 #define CONFIG_BOOTFILE         uImage
 620
 621 #define CONFIG_LOADADDR         800000  /* default location for tftp and bootm */
 622
 623 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 624 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 625
 626 #define CONFIG_BAUDRATE  115200
 627
 628 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 629         "netdev=eth0\0"                                                 \
 630         "hostname=sbc8349\0"                                            \
 631         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 632                 "nfsroot=${serverip}:${rootpath}\0"                     \
 633         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 634         "addip=setenv bootargs ${bootargs} "                            \
 635                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 636                 ":${hostname}:${netdev}:off panic=1\0"                  \
 637         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 638         "flash_nfs=run nfsargs addip addtty;"                           \
 639                 "bootm ${kernel_addr}\0"                                \
 640         "flash_self=run ramargs addip addtty;"                          \
 641                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 642         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 643                 "bootm\0"                                               \
 644         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 645         "update=protect off ff800000 ff83ffff; "                        \
 646                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0"     \
 647         "upd=run load update\0"                                         \
 648         "fdtaddr=780000\0"                                              \
 649         "fdtfile=sbc8349.dtb\0"                                         \
 650         ""
 651
 652 #define CONFIG_NFSBOOTCOMMAND                                           \
 653    "setenv bootargs root=/dev/nfs rw "                                  \
 654       "nfsroot=$serverip:$rootpath "                                    \
 655       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 656       "console=$consoledev,$baudrate $othbootargs;"                     \
 657    "tftp $loadaddr $bootfile;"                                          \
 658    "tftp $fdtaddr $fdtfile;"                                            \
 659    "bootm $loadaddr - $fdtaddr"
 660
 661 #define CONFIG_RAMBOOTCOMMAND                                           \
 662    "setenv bootargs root=/dev/ram rw "                                  \
 663       "console=$consoledev,$baudrate $othbootargs;"                     \
 664    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 665    "tftp $loadaddr $bootfile;"                                          \
 666    "tftp $fdtaddr $fdtfile;"                                            \
 667    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 668
 669 #define CONFIG_BOOTCOMMAND      "run flash_self"
 670
 671 #endif  /* __CONFIG_H */