include/configs/sbc8349.h

   1 /*
   2  * WindRiver SBC8349 U-Boot configuration file.
   3  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   4  *
   5  * Paul Gortmaker <paul.gortmaker@windriver.com>
   6  * Based on the MPC8349EMDS config.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * sbc8349 board configuration file.
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  */
  37 #define CONFIG_E300             1       /* E300 Family */
  38 #define CONFIG_MPC83xx          1       /* MPC83xx family */
  39 #define CONFIG_MPC834x          1       /* MPC834x family */
  40 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  41 #define CONFIG_SBC8349          1       /* WRS SBC8349 board specific */
  42
  43 #undef CONFIG_PCI
  44 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  45 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  46
  47 #define PCI_66M
  48 #ifdef PCI_66M
  49 #define CONFIG_83XX_CLKIN       66000000        /* in Hz */
  50 #else
  51 #define CONFIG_83XX_CLKIN       33000000        /* in Hz */
  52 #endif
  53
  54 #ifndef CONFIG_SYS_CLK_FREQ
  55 #ifdef PCI_66M
  56 #define CONFIG_SYS_CLK_FREQ     66000000
  57 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_4X1
  58 #else
  59 #define CONFIG_SYS_CLK_FREQ     33000000
  60 #define HRCWL_CSB_TO_CLKIN      HRCWL_CSB_TO_CLKIN_8X1
  61 #endif
  62 #endif
  63
  64 #undef CONFIG_BOARD_EARLY_INIT_F                /* call board_pre_init */
  65
  66 #define CONFIG_SYS_IMMR         0xE0000000
  67
  68 #undef CONFIG_SYS_DRAM_TEST                             /* memory test, takes time */
  69 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  70 #define CONFIG_SYS_MEMTEST_END          0x00100000
  71
  72 /*
  73  * DDR Setup
  74  */
  75 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  76 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  77 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  78 #define CONFIG_SYS_83XX_DDR_USES_CS0            /* WRS; Fsl board uses CS2/CS3 */
  79
  80 /*
  81  * 32-bit data path mode.
  82  *
  83  * Please note that using this mode for devices with the real density of 64-bit
  84  * effectively reduces the amount of available memory due to the effect of
  85  * wrapping around while translating address to row/columns, for example in the
  86  * 256MB module the upper 128MB get aliased with contents of the lower
  87  * 128MB); normally this define should be used for devices with real 32-bit
  88  * data path.
  89  */
  90 #undef CONFIG_DDR_32BIT
  91
  92 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  96                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  97 #define CONFIG_DDR_2T_TIMING
  98
  99 #if defined(CONFIG_SPD_EEPROM)
 100 /*
 101  * Determine DDR configuration from I2C interface.
 102  */
 103 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
 104
 105 #else
 106 /*
 107  * Manually set up DDR parameters
 108  * NB: manual DDR setup untested on sbc834x
 109  */
 110 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
 111 #define CONFIG_SYS_DDR_CONFIG           (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 112 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
 113 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
 114 #define CONFIG_SYS_DDR_CONTROL          0xc2000000      /* unbuffered,no DYN_PWR */
 115 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 116
 117 #if defined(CONFIG_DDR_32BIT)
 118 /* set burst length to 8 for 32-bit data path */
 119 #define CONFIG_SYS_DDR_MODE             0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
 120 #else
 121 /* the default burst length is 4 - for 64-bit data path */
 122 #define CONFIG_SYS_DDR_MODE             0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
 123 #endif
 124 #endif
 125
 126 /*
 127  * SDRAM on the Local Bus
 128  */
 129 #define CONFIG_SYS_LBC_SDRAM_BASE       0x10000000      /* Localbus SDRAM */
 130 #define CONFIG_SYS_LBC_SDRAM_SIZE       128             /* LBC SDRAM is 128MB */
 131
 132 /*
 133  * FLASH on the Local Bus
 134  */
 135 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 136 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 137 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 138 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 139 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 140
 141 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
 142                                 (2 << BR_PS_SHIFT) |    /* 32 bit port size */   \
 143                                 BR_V)                   /* valid */
 144
 145 #define CONFIG_SYS_OR0_PRELIM           0xFF806FF7      /* 8 MB flash size */
 146 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE   /* window base at flash base */
 147 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x80000016      /* 8 MB window size */
 148
 149 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 150 #define CONFIG_SYS_MAX_FLASH_SECT       64              /* sectors per device */
 151
 152 #undef CONFIG_SYS_FLASH_CHECKSUM
 153 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 154 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 155
 156 #define CONFIG_SYS_MID_FLASH_JUMP       0x7F000000
 157 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 158
 159 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 160 #define CONFIG_SYS_RAMBOOT
 161 #else
 162 #undef  CONFIG_SYS_RAMBOOT
 163 #endif
 164
 165 #define CONFIG_SYS_INIT_RAM_LOCK        1
 166 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000              /* Initial RAM address */
 167 #define CONFIG_SYS_INIT_RAM_END 0x1000                  /* End of used area in RAM*/
 168
 169 #define CONFIG_SYS_GBL_DATA_SIZE        0x100                   /* num bytes initial data */
 170 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 171 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 172
 173 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)            /* Reserve 256 kB for Mon */
 174 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)            /* Reserved for malloc */
 175
 176 /*
 177  * Local Bus LCRR and LBCR regs
 178  *    LCRR:  DLL bypass, Clock divider is 4
 179  * External Local Bus rate is
 180  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 181  */
 182 #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
 183 #define CONFIG_SYS_LBC_LBCR     0x00000000
 184
 185 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 186
 187 #ifdef CONFIG_SYS_LB_SDRAM
 188 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 189 /*
 190  * Base Register 2 and Option Register 2 configure SDRAM.
 191  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 192  *
 193  * For BR2, need:
 194  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 195  *    port-size = 32-bits = BR2[19:20] = 11
 196  *    no parity checking = BR2[21:22] = 00
 197  *    SDRAM for MSEL = BR2[24:26] = 011
 198  *    Valid = BR[31] = 1
 199  *
 200  * 0    4    8    12   16   20   24   28
 201  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 202  *
 203  * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 204  * FIXME: the top 17 bits of BR2.
 205  */
 206
 207 #define CONFIG_SYS_BR2_PRELIM           0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
 208 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0xF0000000
 209 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x80000019 /* 64M */
 210
 211 /*
 212  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 213  *
 214  * For OR2, need:
 215  *    64MB mask for AM, OR2[0:7] = 1111 1100
 216  *                 XAM, OR2[17:18] = 11
 217  *    9 columns OR2[19-21] = 010
 218  *    13 rows   OR2[23-25] = 100
 219  *    EAD set for extra time OR[31] = 1
 220  *
 221  * 0    4    8    12   16   20   24   28
 222  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 223  */
 224
 225 #define CONFIG_SYS_OR2_PRELIM   0xFC006901
 226
 227 #define CONFIG_SYS_LBC_LSRT     0x32000000    /* LB sdram refresh timer, about 6us */
 228 #define CONFIG_SYS_LBC_MRTPR    0x20000000    /* LB refresh timer prescal, 266MHz/32 */
 229
 230 #define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
 231                                 | LSDMR_BSMA1516        \
 232                                 | LSDMR_RFCR8           \
 233                                 | LSDMR_PRETOACT6       \
 234                                 | LSDMR_ACTTORW3        \
 235                                 | LSDMR_BL8             \
 236                                 | LSDMR_WRC3            \
 237                                 | LSDMR_CL3             \
 238                                 )
 239
 240 /*
 241  * SDRAM Controller configuration sequence.
 242  */
 243 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 244 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 245 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 246 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 247 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 248 #endif
 249
 250 /*
 251  * Serial Port
 252  */
 253 #define CONFIG_CONS_INDEX     1
 254 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 255 #define CONFIG_SYS_NS16550
 256 #define CONFIG_SYS_NS16550_SERIAL
 257 #define CONFIG_SYS_NS16550_REG_SIZE    1
 258 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 259
 260 #define CONFIG_SYS_BAUDRATE_TABLE  \
 261         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 262
 263 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 264 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 265
 266 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 267 /* Use the HUSH parser */
 268 #define CONFIG_SYS_HUSH_PARSER
 269 #ifdef  CONFIG_SYS_HUSH_PARSER
 270 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 271 #endif
 272
 273 /* pass open firmware flat tree */
 274 #define CONFIG_OF_LIBFDT        1
 275 #define CONFIG_OF_BOARD_SETUP   1
 276 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 277
 278 /* I2C */
 279 #define CONFIG_HARD_I2C                 /* I2C with hardware support*/
 280 #undef CONFIG_SOFT_I2C                  /* I2C bit-banged */
 281 #define CONFIG_FSL_I2C
 282 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 283 #define CONFIG_SYS_I2C_SLAVE            0x7F
 284 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 285 #define CONFIG_SYS_I2C1_OFFSET          0x3000
 286 #define CONFIG_SYS_I2C2_OFFSET          0x3100
 287 #define CONFIG_SYS_I2C_OFFSET           CONFIG_SYS_I2C2_OFFSET
 288 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */
 289
 290 /* TSEC */
 291 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 292 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 293 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 294 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 295
 296 /*
 297  * General PCI
 298  * Addresses are mapped 1-1.
 299  */
 300 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 301 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 302 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 303 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 304 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 305 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 306 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 307 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
 308 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000      /* 1M */
 309
 310 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 311 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 312 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 313 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 314 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 315 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 316 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 317 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
 318 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000      /* 1M */
 319
 320 #if defined(CONFIG_PCI)
 321
 322 #define PCI_64BIT
 323 #define PCI_ONE_PCI1
 324 #if defined(PCI_64BIT)
 325 #undef PCI_ALL_PCI1
 326 #undef PCI_TWO_PCI1
 327 #undef PCI_ONE_PCI1
 328 #endif
 329
 330 #define CONFIG_NET_MULTI
 331 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 332
 333 #undef CONFIG_EEPRO100
 334 #undef CONFIG_TULIP
 335
 336 #if !defined(CONFIG_PCI_PNP)
 337         #define PCI_ENET0_IOADDR        0xFIXME
 338         #define PCI_ENET0_MEMADDR       0xFIXME
 339         #define PCI_IDSEL_NUMBER        0xFIXME
 340 #endif
 341
 342 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 343 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 344
 345 #endif  /* CONFIG_PCI */
 346
 347 /*
 348  * TSEC configuration
 349  */
 350 #define CONFIG_TSEC_ENET                /* TSEC ethernet support */
 351
 352 #if defined(CONFIG_TSEC_ENET)
 353 #ifndef CONFIG_NET_MULTI
 354 #define CONFIG_NET_MULTI        1
 355 #endif
 356
 357 #define CONFIG_TSEC1    1
 358 #define CONFIG_TSEC1_NAME       "TSEC0"
 359 #define CONFIG_TSEC2    1
 360 #define CONFIG_TSEC2_NAME       "TSEC1"
 361 #define CONFIG_PHY_BCM5421S     1
 362 #define TSEC1_PHY_ADDR          0x19
 363 #define TSEC2_PHY_ADDR          0x1a
 364 #define TSEC1_PHYIDX            0
 365 #define TSEC2_PHYIDX            0
 366 #define TSEC1_FLAGS             TSEC_GIGABIT
 367 #define TSEC2_FLAGS             TSEC_GIGABIT
 368
 369 /* Options are: TSEC[0-1] */
 370 #define CONFIG_ETHPRIME         "TSEC0"
 371
 372 #endif  /* CONFIG_TSEC_ENET */
 373
 374 /*
 375  * Environment
 376  */
 377 #ifndef CONFIG_SYS_RAMBOOT
 378         #define CONFIG_ENV_IS_IN_FLASH  1
 379         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 380         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 381         #define CONFIG_ENV_SIZE         0x2000
 382
 383 /* Address and size of Redundant Environment Sector     */
 384 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 385 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 386
 387 #else
 388         #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 389         #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 390         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 391         #define CONFIG_ENV_SIZE         0x2000
 392 #endif
 393
 394 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 395 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 396
 397
 398 /*
 399  * BOOTP options
 400  */
 401 #define CONFIG_BOOTP_BOOTFILESIZE
 402 #define CONFIG_BOOTP_BOOTPATH
 403 #define CONFIG_BOOTP_GATEWAY
 404 #define CONFIG_BOOTP_HOSTNAME
 405
 406
 407 /*
 408  * Command line configuration.
 409  */
 410 #include <config_cmd_default.h>
 411
 412 #define CONFIG_CMD_I2C
 413 #define CONFIG_CMD_MII
 414 #define CONFIG_CMD_PING
 415
 416 #if defined(CONFIG_PCI)
 417     #define CONFIG_CMD_PCI
 418 #endif
 419
 420 #if defined(CONFIG_SYS_RAMBOOT)
 421     #undef CONFIG_CMD_SAVEENV
 422     #undef CONFIG_CMD_LOADS
 423 #endif
 424
 425
 426 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 427
 428 /*
 429  * Miscellaneous configurable options
 430  */
 431 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 432 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 433 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 434
 435 #if defined(CONFIG_CMD_KGDB)
 436         #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 437 #else
 438         #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 439 #endif
 440
 441 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 442 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 443 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 444 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 445
 446 /*
 447  * For booting Linux, the board info and command line data
 448  * have to be in the first 8 MB of memory, since this is
 449  * the maximum mapped by the Linux kernel during initialization.
 450  */
 451 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 452
 453 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 454
 455 #if 1 /*528/264*/
 456 #define CONFIG_SYS_HRCW_LOW (\
 457         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 458         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 459         HRCWL_CSB_TO_CLKIN |\
 460         HRCWL_VCO_1X2 |\
 461         HRCWL_CORE_TO_CSB_2X1)
 462 #elif 0 /*396/132*/
 463 #define CONFIG_SYS_HRCW_LOW (\
 464         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 465         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 466         HRCWL_CSB_TO_CLKIN |\
 467         HRCWL_VCO_1X4 |\
 468         HRCWL_CORE_TO_CSB_3X1)
 469 #elif 0 /*264/132*/
 470 #define CONFIG_SYS_HRCW_LOW (\
 471         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 472         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 473         HRCWL_CSB_TO_CLKIN |\
 474         HRCWL_VCO_1X4 |\
 475         HRCWL_CORE_TO_CSB_2X1)
 476 #elif 0 /*132/132*/
 477 #define CONFIG_SYS_HRCW_LOW (\
 478         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 479         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 480         HRCWL_CSB_TO_CLKIN |\
 481         HRCWL_VCO_1X4 |\
 482         HRCWL_CORE_TO_CSB_1X1)
 483 #elif 0 /*264/264 */
 484 #define CONFIG_SYS_HRCW_LOW (\
 485         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 486         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 487         HRCWL_CSB_TO_CLKIN |\
 488         HRCWL_VCO_1X4 |\
 489         HRCWL_CORE_TO_CSB_1X1)
 490 #endif
 491
 492 #if defined(PCI_64BIT)
 493 #define CONFIG_SYS_HRCW_HIGH (\
 494         HRCWH_PCI_HOST |\
 495         HRCWH_64_BIT_PCI |\
 496         HRCWH_PCI1_ARBITER_ENABLE |\
 497         HRCWH_PCI2_ARBITER_DISABLE |\
 498         HRCWH_CORE_ENABLE |\
 499         HRCWH_FROM_0X00000100 |\
 500         HRCWH_BOOTSEQ_DISABLE |\
 501         HRCWH_SW_WATCHDOG_DISABLE |\
 502         HRCWH_ROM_LOC_LOCAL_16BIT |\
 503         HRCWH_TSEC1M_IN_GMII |\
 504         HRCWH_TSEC2M_IN_GMII )
 505 #else
 506 #define CONFIG_SYS_HRCW_HIGH (\
 507         HRCWH_PCI_HOST |\
 508         HRCWH_32_BIT_PCI |\
 509         HRCWH_PCI1_ARBITER_ENABLE |\
 510         HRCWH_PCI2_ARBITER_ENABLE |\
 511         HRCWH_CORE_ENABLE |\
 512         HRCWH_FROM_0X00000100 |\
 513         HRCWH_BOOTSEQ_DISABLE |\
 514         HRCWH_SW_WATCHDOG_DISABLE |\
 515         HRCWH_ROM_LOC_LOCAL_16BIT |\
 516         HRCWH_TSEC1M_IN_GMII |\
 517         HRCWH_TSEC2M_IN_GMII )
 518 #endif
 519
 520 /* System IO Config */
 521 #define CONFIG_SYS_SICRH 0
 522 #define CONFIG_SYS_SICRL SICRL_LDP_A
 523
 524 #define CONFIG_SYS_HID0_INIT    0x000000000
 525 #define CONFIG_SYS_HID0_FINAL   HID0_ENABLE_MACHINE_CHECK
 526
 527 /* #define CONFIG_SYS_HID0_FINAL                (\
 528         HID0_ENABLE_INSTRUCTION_CACHE |\
 529         HID0_ENABLE_M_BIT |\
 530         HID0_ENABLE_ADDRESS_BROADCAST ) */
 531
 532
 533 #define CONFIG_SYS_HID2 HID2_HBE
 534
 535 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 536
 537 /* DDR @ 0x00000000 */
 538 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 539 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 540
 541 /* PCI @ 0x80000000 */
 542 #ifdef CONFIG_PCI
 543 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 544 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 545 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 546 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 547 #else
 548 #define CONFIG_SYS_IBAT1L       (0)
 549 #define CONFIG_SYS_IBAT1U       (0)
 550 #define CONFIG_SYS_IBAT2L       (0)
 551 #define CONFIG_SYS_IBAT2U       (0)
 552 #endif
 553
 554 #ifdef CONFIG_MPC83XX_PCI2
 555 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 556 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 557 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 558 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 559 #else
 560 #define CONFIG_SYS_IBAT3L       (0)
 561 #define CONFIG_SYS_IBAT3U       (0)
 562 #define CONFIG_SYS_IBAT4L       (0)
 563 #define CONFIG_SYS_IBAT4U       (0)
 564 #endif
 565
 566 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 567 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 568 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
 569
 570 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 571 #define CONFIG_SYS_IBAT6L       (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
 572                                  BATL_GUARDEDSTORAGE)
 573 #define CONFIG_SYS_IBAT6U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 574
 575 #define CONFIG_SYS_IBAT7L       (0)
 576 #define CONFIG_SYS_IBAT7U       (0)
 577
 578 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 579 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 580 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 581 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 582 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 583 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 584 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 585 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 586 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 587 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 588 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 589 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 590 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 591 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 592 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 593 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 594
 595 /*
 596  * Internal Definitions
 597  *
 598  * Boot Flags
 599  */
 600 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 601 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 602
 603 #if defined(CONFIG_CMD_KGDB)
 604 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 605 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 606 #endif
 607
 608 /*
 609  * Environment Configuration
 610  */
 611 #define CONFIG_ENV_OVERWRITE
 612
 613 #if defined(CONFIG_TSEC_ENET)
 614 #define CONFIG_HAS_ETH0
 615 #define CONFIG_ETHADDR          00:a0:1e:a0:13:8d
 616 #define CONFIG_HAS_ETH1
 617 #define CONFIG_ETH1ADDR         00:a0:1e:a0:13:8e
 618 #endif
 619
 620 #define CONFIG_IPADDR           192.168.1.234
 621
 622 #define CONFIG_HOSTNAME         SBC8349
 623 #define CONFIG_ROOTPATH         /tftpboot/rootfs
 624 #define CONFIG_BOOTFILE         uImage
 625
 626 #define CONFIG_SERVERIP         192.168.1.1
 627 #define CONFIG_GATEWAYIP        192.168.1.1
 628 #define CONFIG_NETMASK          255.255.255.0
 629
 630 #define CONFIG_LOADADDR         500000  /* default location for tftp and bootm */
 631
 632 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 633 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 634
 635 #define CONFIG_BAUDRATE  115200
 636
 637 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 638         "netdev=eth0\0"                                                 \
 639         "hostname=sbc8349\0"                                            \
 640         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 641                 "nfsroot=${serverip}:${rootpath}\0"                     \
 642         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 643         "addip=setenv bootargs ${bootargs} "                            \
 644                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 645                 ":${hostname}:${netdev}:off panic=1\0"                  \
 646         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 647         "flash_nfs=run nfsargs addip addtty;"                           \
 648                 "bootm ${kernel_addr}\0"                                \
 649         "flash_self=run ramargs addip addtty;"                          \
 650                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 651         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 652                 "bootm\0"                                               \
 653         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 654         "update=protect off ff800000 ff83ffff; "                        \
 655                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0"     \
 656         "upd=run load update\0"                                         \
 657         "fdtaddr=400000\0"                                              \
 658         "fdtfile=sbc8349.dtb\0"                                         \
 659         ""
 660
 661 #define CONFIG_NFSBOOTCOMMAND                                           \
 662    "setenv bootargs root=/dev/nfs rw "                                  \
 663       "nfsroot=$serverip:$rootpath "                                    \
 664       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 665       "console=$consoledev,$baudrate $othbootargs;"                     \
 666    "tftp $loadaddr $bootfile;"                                          \
 667    "tftp $fdtaddr $fdtfile;"                                            \
 668    "bootm $loadaddr - $fdtaddr"
 669
 670 #define CONFIG_RAMBOOTCOMMAND                                           \
 671    "setenv bootargs root=/dev/ram rw "                                  \
 672       "console=$consoledev,$baudrate $othbootargs;"                     \
 673    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 674    "tftp $loadaddr $bootfile;"                                          \
 675    "tftp $fdtaddr $fdtfile;"                                            \
 676    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 677
 678 #define CONFIG_BOOTCOMMAND      "run flash_self"
 679
 680 #endif  /* __CONFIG_H */