include/configs/sbc8548.h

   1 /*
   2  * Copyright 2007,2009 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Copyright 2004, 2007 Freescale Semiconductor.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * sbc8548 board configuration file
  11  * Please refer to doc/README.sbc8548 for more info.
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16
  17 /*
  18  * Top level Makefile configuration choices
  19  */
  20 #ifdef CONFIG_PCI
  21 #define CONFIG_PCI_INDIRECT_BRIDGE
  22 #define CONFIG_PCI1
  23 #endif
  24
  25 #ifdef CONFIG_66
  26 #define CONFIG_SYS_CLK_DIV 1
  27 #endif
  28
  29 #ifdef CONFIG_33
  30 #define CONFIG_SYS_CLK_DIV 2
  31 #endif
  32
  33 #ifdef CONFIG_PCIE
  34 #define CONFIG_PCIE1
  35 #endif
  36
  37 /*
  38  * High Level Configuration Options
  39  */
  40 #define CONFIG_BOOKE            1       /* BOOKE */
  41 #define CONFIG_E500             1       /* BOOKE e500 family */
  42 #define CONFIG_MPC8548          1       /* MPC8548 specific */
  43 #define CONFIG_SBC8548          1       /* SBC8548 board specific */
  44
  45 /*
  46  * If you want to boot from the SODIMM flash, instead of the soldered
  47  * on flash, set this, and change JP12, SW2:8 accordingly.
  48  */
  49 #undef CONFIG_SYS_ALT_BOOT
  50
  51 #ifndef CONFIG_SYS_TEXT_BASE
  52 #ifdef CONFIG_SYS_ALT_BOOT
  53 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  54 #else
  55 #define CONFIG_SYS_TEXT_BASE    0xfffa0000
  56 #endif
  57 #endif
  58
  59 #undef CONFIG_RIO
  60
  61 #ifdef CONFIG_PCI
  62 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  63 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  64 #endif
  65 #ifdef CONFIG_PCIE1
  66 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  67 #endif
  68
  69 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  70 #define CONFIG_ENV_OVERWRITE
  71
  72 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  73
  74 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  75
  76 /*
  77  * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
  78  */
  79 #ifndef CONFIG_SYS_CLK_DIV
  80 #define CONFIG_SYS_CLK_DIV      1       /* 2, if 33MHz PCI card installed */
  81 #endif
  82 #define CONFIG_SYS_CLK_FREQ     (66000000 / CONFIG_SYS_CLK_DIV)
  83
  84 /*
  85  * These can be toggled for performance analysis, otherwise use default.
  86  */
  87 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  88 #define CONFIG_BTB                      /* toggle branch predition */
  89
  90 /*
  91  * Only possible on E500 Version 2 or newer cores.
  92  */
  93 #define CONFIG_ENABLE_36BIT_PHYS        1
  94
  95 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  96
  97 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  98 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  99 #define CONFIG_SYS_MEMTEST_END          0x00400000
 100
 101 #define CONFIG_SYS_CCSRBAR              0xe0000000
 102 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 103
 104 /* DDR Setup */
 105 #define CONFIG_SYS_FSL_DDR2
 106 #undef CONFIG_FSL_DDR_INTERACTIVE
 107 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
 108 /*
 109  * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
 110  * to collide, meaning you couldn't reliably read either. So
 111  * physically remove the LBC PC100 SDRAM module from the board
 112  * before enabling the two SPD options below, or check that you
 113  * have the hardware fix on your board via "i2c probe" and looking
 114  * for a device at 0x53.
 115  */
 116 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
 117 #undef CONFIG_DDR_SPD
 118
 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 120 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 121
 122 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 123 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 124 #define CONFIG_VERY_BIG_RAM
 125
 126 #define CONFIG_NUM_DDR_CONTROLLERS      1
 127 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 128 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 129
 130 /*
 131  * The hardware fix for the I2C address collision puts the DDR
 132  * SPD at 0x53, but if we are running on an older board w/o the
 133  * fix, it will still be at 0x51.  We check 0x53 1st.
 134  */
 135 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 136 #define ALT_SPD_EEPROM_ADDRESS  0x53    /* CTLR 0 DIMM 0 */
 137
 138 /*
 139  * Make sure required options are set
 140  */
 141 #ifndef CONFIG_SPD_EEPROM
 142         #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 143         #define CONFIG_SYS_DDR_CONTROL  0xc300c000
 144 #endif
 145
 146 #undef CONFIG_CLOCKS_IN_MHZ
 147
 148 /*
 149  * FLASH on the Local Bus
 150  * Two banks, one 8MB the other 64MB, using the CFI driver.
 151  * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
 152  * CS0 the 8MB boot flash, and CS6 the 64MB flash.
 153  *
 154  *      Default:
 155  *      ec00_0000       efff_ffff       64MB SODIMM
 156  *      ff80_0000       ffff_ffff       8MB soldered flash
 157  *
 158  *      Alternate:
 159  *      ef80_0000       efff_ffff       8MB soldered flash
 160  *      fc00_0000       ffff_ffff       64MB SODIMM
 161  *
 162  * BR0_8M:
 163  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
 164  *    Port Size = 8 bits = BRx[19:20] = 01
 165  *    Use GPCM = BRx[24:26] = 000
 166  *    Valid = BRx[31] = 1
 167  *
 168  * BR0_64M:
 169  *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
 170  *    Port Size = 32 bits = BRx[19:20] = 11
 171  *
 172  * 0    4    8    12   16   20   24   28
 173  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
 174  * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
 175  */
 176 #define CONFIG_SYS_BR0_8M       0xff800801
 177 #define CONFIG_SYS_BR0_64M      0xfc001801
 178
 179 /*
 180  * BR6_8M:
 181  *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
 182  *    Port Size = 8 bits = BRx[19:20] = 01
 183  *    Use GPCM = BRx[24:26] = 000
 184  *    Valid = BRx[31] = 1
 185
 186  * BR6_64M:
 187  *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
 188  *    Port Size = 32 bits = BRx[19:20] = 11
 189  *
 190  * 0    4    8    12   16   20   24   28
 191  * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
 192  * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
 193  */
 194 #define CONFIG_SYS_BR6_8M       0xef800801
 195 #define CONFIG_SYS_BR6_64M      0xec001801
 196
 197 /*
 198  * OR0_8M:
 199  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
 200  *    XAM = OR0[17:18] = 11
 201  *    CSNT = OR0[20] = 1
 202  *    ACS = half cycle delay = OR0[21:22] = 11
 203  *    SCY = 6 = OR0[24:27] = 0110
 204  *    TRLX = use relaxed timing = OR0[29] = 1
 205  *    EAD = use external address latch delay = OR0[31] = 1
 206  *
 207  * OR0_64M:
 208  *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
 209  *
 210  *
 211  * 0    4    8    12   16   20   24   28
 212  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
 213  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
 214  */
 215 #define CONFIG_SYS_OR0_8M       0xff806e65
 216 #define CONFIG_SYS_OR0_64M      0xfc006e65
 217
 218 /*
 219  * OR6_8M:
 220  *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
 221  *    XAM = OR6[17:18] = 11
 222  *    CSNT = OR6[20] = 1
 223  *    ACS = half cycle delay = OR6[21:22] = 11
 224  *    SCY = 6 = OR6[24:27] = 0110
 225  *    TRLX = use relaxed timing = OR6[29] = 1
 226  *    EAD = use external address latch delay = OR6[31] = 1
 227  *
 228  * OR6_64M:
 229  *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
 230  *
 231  * 0    4    8    12   16   20   24   28
 232  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
 233  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
 234  */
 235 #define CONFIG_SYS_OR6_8M       0xff806e65
 236 #define CONFIG_SYS_OR6_64M      0xfc006e65
 237
 238 #ifndef CONFIG_SYS_ALT_BOOT             /* JP12 in default position */
 239 #define CONFIG_SYS_BOOT_BLOCK           0xff800000      /* start of 8MB Flash */
 240 #define CONFIG_SYS_ALT_FLASH            0xec000000      /* 64MB "user" flash */
 241
 242 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_8M
 243 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_8M
 244
 245 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_64M
 246 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_64M
 247 #else                                   /* JP12 in alternate position */
 248 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* start 64MB Flash */
 249 #define CONFIG_SYS_ALT_FLASH            0xef800000      /* 8MB soldered flash */
 250
 251 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_64M
 252 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_64M
 253
 254 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_8M
 255 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_8M
 256 #endif
 257
 258 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK
 259 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, \
 260                                          CONFIG_SYS_ALT_FLASH}
 261 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 262 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device */
 263 #undef  CONFIG_SYS_FLASH_CHECKSUM
 264 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 265 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 266
 267 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 268
 269 #define CONFIG_FLASH_CFI_DRIVER
 270 #define CONFIG_SYS_FLASH_CFI
 271 #define CONFIG_SYS_FLASH_EMPTY_INFO
 272
 273 /* CS5 = Local bus peripherals controlled by the EPLD */
 274
 275 #define CONFIG_SYS_BR5_PRELIM           0xf8000801
 276 #define CONFIG_SYS_OR5_PRELIM           0xff006e65
 277 #define CONFIG_SYS_EPLD_BASE            0xf8000000
 278 #define CONFIG_SYS_LED_DISP_BASE        0xf8000000
 279 #define CONFIG_SYS_USER_SWITCHES_BASE   0xf8100000
 280 #define CONFIG_SYS_BD_REV               0xf8300000
 281 #define CONFIG_SYS_EEPROM_BASE          0xf8b00000
 282
 283 /*
 284  * SDRAM on the Local Bus (CS3 and CS4)
 285  * Note that most boards have a hardware errata where both the
 286  * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
 287  * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
 288  * A hardware workaround is also available, see README.sbc8548 file.
 289  */
 290 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 291 #define CONFIG_SYS_LBC_SDRAM_SIZE       128             /* LBC SDRAM is 128MB */
 292
 293 /*
 294  * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
 295  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 296  *
 297  * For BR3, need:
 298  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 299  *    port-size = 32-bits = BR2[19:20] = 11
 300  *    no parity checking = BR2[21:22] = 00
 301  *    SDRAM for MSEL = BR2[24:26] = 011
 302  *    Valid = BR[31] = 1
 303  *
 304  * 0    4    8    12   16   20   24   28
 305  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 306  *
 307  */
 308
 309 #define CONFIG_SYS_BR3_PRELIM           0xf0001861
 310
 311 /*
 312  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 313  *
 314  * For OR3, need:
 315  *    64MB mask for AM, OR3[0:7] = 1111 1100
 316  *                 XAM, OR3[17:18] = 11
 317  *    10 columns OR3[19-21] = 011
 318  *    12 rows   OR3[23-25] = 011
 319  *    EAD set for extra time OR[31] = 0
 320  *
 321  * 0    4    8    12   16   20   24   28
 322  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 323  */
 324
 325 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0
 326
 327 /*
 328  * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
 329  * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
 330  *
 331  * For BR4, need:
 332  *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
 333  *    port-size = 32-bits = BR2[19:20] = 11
 334  *    no parity checking = BR2[21:22] = 00
 335  *    SDRAM for MSEL = BR2[24:26] = 011
 336  *    Valid = BR[31] = 1
 337  *
 338  * 0    4    8    12   16   20   24   28
 339  * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
 340  *
 341  */
 342
 343 #define CONFIG_SYS_BR4_PRELIM           0xf4001861
 344
 345 /*
 346  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 347  *
 348  * For OR4, need:
 349  *    64MB mask for AM, OR3[0:7] = 1111 1100
 350  *                 XAM, OR3[17:18] = 11
 351  *    10 columns OR3[19-21] = 011
 352  *    12 rows   OR3[23-25] = 011
 353  *    EAD set for extra time OR[31] = 0
 354  *
 355  * 0    4    8    12   16   20   24   28
 356  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 357  */
 358
 359 #define CONFIG_SYS_OR4_PRELIM           0xfc006cc0
 360
 361 #define CONFIG_SYS_LBC_LCRR             0x00000002    /* LB clock ratio reg */
 362 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 363 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 364 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 365
 366 /*
 367  * Common settings for all Local Bus SDRAM commands.
 368  */
 369 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 370                                 | LSDMR_BSMA1516        \
 371                                 | LSDMR_PRETOACT3       \
 372                                 | LSDMR_ACTTORW3        \
 373                                 | LSDMR_BUFCMD          \
 374                                 | LSDMR_BL8             \
 375                                 | LSDMR_WRC2            \
 376                                 | LSDMR_CL3             \
 377                                 )
 378
 379 #define CONFIG_SYS_LBC_LSDMR_PCHALL     \
 380          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 381 #define CONFIG_SYS_LBC_LSDMR_ARFRSH     \
 382          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 383 #define CONFIG_SYS_LBC_LSDMR_MRW        \
 384          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 385 #define CONFIG_SYS_LBC_LSDMR_RFEN       \
 386          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
 387
 388 #define CONFIG_SYS_INIT_RAM_LOCK        1
 389 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 390 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 391
 392 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 393
 394 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 395 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 396
 397 /*
 398  * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
 399  * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
 400  * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
 401  * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
 402  * thing for MONITOR_LEN in both cases.
 403  */
 404 #define CONFIG_SYS_MONITOR_LEN          (~CONFIG_SYS_TEXT_BASE + 1)
 405 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024) /* Reserved for malloc */
 406
 407 /* Serial Port */
 408 #define CONFIG_CONS_INDEX       1
 409 #define CONFIG_SYS_NS16550_SERIAL
 410 #define CONFIG_SYS_NS16550_REG_SIZE     1
 411 #define CONFIG_SYS_NS16550_CLK          (400000000 / CONFIG_SYS_CLK_DIV)
 412
 413 #define CONFIG_SYS_BAUDRATE_TABLE \
 414         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 415
 416 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 417 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 418
 419 /* Use the HUSH parser */
 420 #define CONFIG_SYS_HUSH_PARSER
 421
 422 /*
 423  * I2C
 424  */
 425 #define CONFIG_SYS_I2C
 426 #define CONFIG_SYS_I2C_FSL
 427 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 428 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 429 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 430 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 431
 432 /*
 433  * General PCI
 434  * Memory space is mapped 1-1, but I/O space must start from 0.
 435  */
 436 #define CONFIG_SYS_PCI_VIRT             0x80000000      /* 1G PCI TLB */
 437 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 438
 439 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 440 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 441 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 442 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 443 #define CONFIG_SYS_PCI1_IO_VIRT         0xe2000000
 444 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 445 #define CONFIG_SYS_PCI1_IO_PHYS         0xe2000000
 446 #define CONFIG_SYS_PCI1_IO_SIZE         0x00800000      /* 8M */
 447
 448 #ifdef CONFIG_PCIE1
 449 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 450 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 451 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 452 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 453 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 454 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 455 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 456 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 457 #endif
 458
 459 #ifdef CONFIG_RIO
 460 /*
 461  * RapidIO MMU
 462  */
 463 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
 464 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 465 #endif
 466
 467 #if defined(CONFIG_PCI)
 468
 469 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 470
 471 #undef CONFIG_EEPRO100
 472 #undef CONFIG_TULIP
 473
 474 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 475
 476 #endif  /* CONFIG_PCI */
 477
 478
 479 #if defined(CONFIG_TSEC_ENET)
 480
 481 #define CONFIG_MII              1       /* MII PHY management */
 482 #define CONFIG_TSEC1    1
 483 #define CONFIG_TSEC1_NAME       "eTSEC0"
 484 #define CONFIG_TSEC2    1
 485 #define CONFIG_TSEC2_NAME       "eTSEC1"
 486 #undef CONFIG_MPC85XX_FEC
 487
 488 #define TSEC1_PHY_ADDR          0x19
 489 #define TSEC2_PHY_ADDR          0x1a
 490
 491 #define TSEC1_PHYIDX            0
 492 #define TSEC2_PHYIDX            0
 493
 494 #define TSEC1_FLAGS             TSEC_GIGABIT
 495 #define TSEC2_FLAGS             TSEC_GIGABIT
 496
 497 /* Options are: eTSEC[0-3] */
 498 #define CONFIG_ETHPRIME         "eTSEC0"
 499 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 500 #endif  /* CONFIG_TSEC_ENET */
 501
 502 /*
 503  * Environment
 504  */
 505 #define CONFIG_ENV_IS_IN_FLASH  1
 506 #define CONFIG_ENV_SIZE         0x2000
 507 #if CONFIG_SYS_TEXT_BASE == 0xfff00000  /* Boot from 64MB SODIMM */
 508 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x80000)
 509 #define CONFIG_ENV_SECT_SIZE    0x80000 /* 512K(one sector) for env */
 510 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000        /* Boot from 8MB soldered flash */
 511 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 512 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 513 #else
 514 #warning undefined environment size/location.
 515 #endif
 516
 517 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 518 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 519
 520 /*
 521  * BOOTP options
 522  */
 523 #define CONFIG_BOOTP_BOOTFILESIZE
 524 #define CONFIG_BOOTP_BOOTPATH
 525 #define CONFIG_BOOTP_GATEWAY
 526 #define CONFIG_BOOTP_HOSTNAME
 527
 528
 529 /*
 530  * Command line configuration.
 531  */
 532 #define CONFIG_CMD_PING
 533 #define CONFIG_CMD_I2C
 534 #define CONFIG_CMD_MII
 535 #define CONFIG_CMD_REGINFO
 536
 537 #if defined(CONFIG_PCI)
 538     #define CONFIG_CMD_PCI
 539 #endif
 540
 541
 542 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 543
 544 /*
 545  * Miscellaneous configurable options
 546  */
 547 #define CONFIG_CMDLINE_EDITING                  /* undef to save memory */
 548 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 549 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 550 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 551 #if defined(CONFIG_CMD_KGDB)
 552 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 553 #else
 554 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 555 #endif
 556 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 557 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 558 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 559
 560 /*
 561  * For booting Linux, the board info and command line data
 562  * have to be in the first 8 MB of memory, since this is
 563  * the maximum mapped by the Linux kernel during initialization.
 564  */
 565 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 566
 567 #if defined(CONFIG_CMD_KGDB)
 568 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 569 #endif
 570
 571 /*
 572  * Environment Configuration
 573  */
 574 #if defined(CONFIG_TSEC_ENET)
 575 #define CONFIG_HAS_ETH0
 576 #define CONFIG_HAS_ETH1
 577 #endif
 578
 579 #define CONFIG_IPADDR    192.168.0.55
 580
 581 #define CONFIG_HOSTNAME  sbc8548
 582 #define CONFIG_ROOTPATH  "/opt/eldk/ppc_85xx"
 583 #define CONFIG_BOOTFILE  "/uImage"
 584 #define CONFIG_UBOOTPATH /u-boot.bin    /* TFTP server */
 585
 586 #define CONFIG_SERVERIP  192.168.0.2
 587 #define CONFIG_GATEWAYIP 192.168.0.1
 588 #define CONFIG_NETMASK   255.255.255.0
 589
 590 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 591
 592 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 593 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 594
 595 #define CONFIG_BAUDRATE 115200
 596
 597 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 598 "netdev=eth0\0"                                         \
 599 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                             \
 600 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 601         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 602         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 603         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 604         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 605         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 606 "consoledev=ttyS0\0"                            \
 607 "ramdiskaddr=2000000\0"                 \
 608 "ramdiskfile=uRamdisk\0"                        \
 609 "fdtaddr=c00000\0"                              \
 610 "fdtfile=sbc8548.dtb\0"
 611
 612 #define CONFIG_NFSBOOTCOMMAND                                           \
 613    "setenv bootargs root=/dev/nfs rw "                                  \
 614       "nfsroot=$serverip:$rootpath "                                    \
 615       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 616       "console=$consoledev,$baudrate $othbootargs;"                     \
 617    "tftp $loadaddr $bootfile;"                                          \
 618    "tftp $fdtaddr $fdtfile;"                                            \
 619    "bootm $loadaddr - $fdtaddr"
 620
 621
 622 #define CONFIG_RAMBOOTCOMMAND \
 623    "setenv bootargs root=/dev/ram rw "                                  \
 624       "console=$consoledev,$baudrate $othbootargs;"                     \
 625    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 626    "tftp $loadaddr $bootfile;"                                          \
 627    "tftp $fdtaddr $fdtfile;"                                            \
 628    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 629
 630 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 631
 632 #endif  /* __CONFIG_H */