include/configs/sbc8548.h

   1 /*
   2  * Copyright 2007,2009 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Copyright 2004, 2007 Freescale Semiconductor.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * sbc8548 board configuration file
  11  * Please refer to doc/README.sbc8548 for more info.
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * Top level Makefile configuration choices
  18  */
  19 #ifdef CONFIG_PCI
  20 #define CONFIG_PCI_INDIRECT_BRIDGE
  21 #define CONFIG_PCI1
  22 #endif
  23
  24 #ifdef CONFIG_66
  25 #define CONFIG_SYS_CLK_DIV 1
  26 #endif
  27
  28 #ifdef CONFIG_33
  29 #define CONFIG_SYS_CLK_DIV 2
  30 #endif
  31
  32 #ifdef CONFIG_PCIE
  33 #define CONFIG_PCIE1
  34 #endif
  35
  36 /*
  37  * High Level Configuration Options
  38  */
  39 #define CONFIG_SBC8548          1       /* SBC8548 board specific */
  40
  41 /*
  42  * If you want to boot from the SODIMM flash, instead of the soldered
  43  * on flash, set this, and change JP12, SW2:8 accordingly.
  44  */
  45 #undef CONFIG_SYS_ALT_BOOT
  46
  47 #ifndef CONFIG_SYS_TEXT_BASE
  48 #ifdef CONFIG_SYS_ALT_BOOT
  49 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  50 #else
  51 #define CONFIG_SYS_TEXT_BASE    0xfffa0000
  52 #endif
  53 #endif
  54
  55 #undef CONFIG_RIO
  56
  57 #ifdef CONFIG_PCI
  58 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  59 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  60 #endif
  61 #ifdef CONFIG_PCIE1
  62 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  63 #endif
  64
  65 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  66 #define CONFIG_ENV_OVERWRITE
  67
  68 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  69
  70 /*
  71  * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
  72  */
  73 #ifndef CONFIG_SYS_CLK_DIV
  74 #define CONFIG_SYS_CLK_DIV      1       /* 2, if 33MHz PCI card installed */
  75 #endif
  76 #define CONFIG_SYS_CLK_FREQ     (66000000 / CONFIG_SYS_CLK_DIV)
  77
  78 /*
  79  * These can be toggled for performance analysis, otherwise use default.
  80  */
  81 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  82 #define CONFIG_BTB                      /* toggle branch predition */
  83
  84 /*
  85  * Only possible on E500 Version 2 or newer cores.
  86  */
  87 #define CONFIG_ENABLE_36BIT_PHYS        1
  88
  89 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  90 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  91 #define CONFIG_SYS_MEMTEST_END          0x00400000
  92
  93 #define CONFIG_SYS_CCSRBAR              0xe0000000
  94 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  95
  96 /* DDR Setup */
  97 #undef CONFIG_FSL_DDR_INTERACTIVE
  98 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  99 /*
 100  * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
 101  * to collide, meaning you couldn't reliably read either. So
 102  * physically remove the LBC PC100 SDRAM module from the board
 103  * before enabling the two SPD options below, or check that you
 104  * have the hardware fix on your board via "i2c probe" and looking
 105  * for a device at 0x53.
 106  */
 107 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
 108 #undef CONFIG_DDR_SPD
 109
 110 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 111 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 112
 113 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 114 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 115 #define CONFIG_VERY_BIG_RAM
 116
 117 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 118 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 119
 120 /*
 121  * The hardware fix for the I2C address collision puts the DDR
 122  * SPD at 0x53, but if we are running on an older board w/o the
 123  * fix, it will still be at 0x51.  We check 0x53 1st.
 124  */
 125 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 126 #define ALT_SPD_EEPROM_ADDRESS  0x53    /* CTLR 0 DIMM 0 */
 127
 128 /*
 129  * Make sure required options are set
 130  */
 131 #ifndef CONFIG_SPD_EEPROM
 132         #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 133         #define CONFIG_SYS_DDR_CONTROL  0xc300c000
 134 #endif
 135
 136 #undef CONFIG_CLOCKS_IN_MHZ
 137
 138 /*
 139  * FLASH on the Local Bus
 140  * Two banks, one 8MB the other 64MB, using the CFI driver.
 141  * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
 142  * CS0 the 8MB boot flash, and CS6 the 64MB flash.
 143  *
 144  *      Default:
 145  *      ec00_0000       efff_ffff       64MB SODIMM
 146  *      ff80_0000       ffff_ffff       8MB soldered flash
 147  *
 148  *      Alternate:
 149  *      ef80_0000       efff_ffff       8MB soldered flash
 150  *      fc00_0000       ffff_ffff       64MB SODIMM
 151  *
 152  * BR0_8M:
 153  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
 154  *    Port Size = 8 bits = BRx[19:20] = 01
 155  *    Use GPCM = BRx[24:26] = 000
 156  *    Valid = BRx[31] = 1
 157  *
 158  * BR0_64M:
 159  *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
 160  *    Port Size = 32 bits = BRx[19:20] = 11
 161  *
 162  * 0    4    8    12   16   20   24   28
 163  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
 164  * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
 165  */
 166 #define CONFIG_SYS_BR0_8M       0xff800801
 167 #define CONFIG_SYS_BR0_64M      0xfc001801
 168
 169 /*
 170  * BR6_8M:
 171  *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
 172  *    Port Size = 8 bits = BRx[19:20] = 01
 173  *    Use GPCM = BRx[24:26] = 000
 174  *    Valid = BRx[31] = 1
 175
 176  * BR6_64M:
 177  *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
 178  *    Port Size = 32 bits = BRx[19:20] = 11
 179  *
 180  * 0    4    8    12   16   20   24   28
 181  * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
 182  * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
 183  */
 184 #define CONFIG_SYS_BR6_8M       0xef800801
 185 #define CONFIG_SYS_BR6_64M      0xec001801
 186
 187 /*
 188  * OR0_8M:
 189  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
 190  *    XAM = OR0[17:18] = 11
 191  *    CSNT = OR0[20] = 1
 192  *    ACS = half cycle delay = OR0[21:22] = 11
 193  *    SCY = 6 = OR0[24:27] = 0110
 194  *    TRLX = use relaxed timing = OR0[29] = 1
 195  *    EAD = use external address latch delay = OR0[31] = 1
 196  *
 197  * OR0_64M:
 198  *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
 199  *
 200  *
 201  * 0    4    8    12   16   20   24   28
 202  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
 203  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
 204  */
 205 #define CONFIG_SYS_OR0_8M       0xff806e65
 206 #define CONFIG_SYS_OR0_64M      0xfc006e65
 207
 208 /*
 209  * OR6_8M:
 210  *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
 211  *    XAM = OR6[17:18] = 11
 212  *    CSNT = OR6[20] = 1
 213  *    ACS = half cycle delay = OR6[21:22] = 11
 214  *    SCY = 6 = OR6[24:27] = 0110
 215  *    TRLX = use relaxed timing = OR6[29] = 1
 216  *    EAD = use external address latch delay = OR6[31] = 1
 217  *
 218  * OR6_64M:
 219  *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
 220  *
 221  * 0    4    8    12   16   20   24   28
 222  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
 223  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
 224  */
 225 #define CONFIG_SYS_OR6_8M       0xff806e65
 226 #define CONFIG_SYS_OR6_64M      0xfc006e65
 227
 228 #ifndef CONFIG_SYS_ALT_BOOT             /* JP12 in default position */
 229 #define CONFIG_SYS_BOOT_BLOCK           0xff800000      /* start of 8MB Flash */
 230 #define CONFIG_SYS_ALT_FLASH            0xec000000      /* 64MB "user" flash */
 231
 232 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_8M
 233 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_8M
 234
 235 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_64M
 236 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_64M
 237 #else                                   /* JP12 in alternate position */
 238 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* start 64MB Flash */
 239 #define CONFIG_SYS_ALT_FLASH            0xef800000      /* 8MB soldered flash */
 240
 241 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_64M
 242 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_64M
 243
 244 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_8M
 245 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_8M
 246 #endif
 247
 248 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK
 249 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, \
 250                                          CONFIG_SYS_ALT_FLASH}
 251 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 252 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device */
 253 #undef  CONFIG_SYS_FLASH_CHECKSUM
 254 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 255 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 256
 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 258
 259 #define CONFIG_FLASH_CFI_DRIVER
 260 #define CONFIG_SYS_FLASH_CFI
 261 #define CONFIG_SYS_FLASH_EMPTY_INFO
 262
 263 /* CS5 = Local bus peripherals controlled by the EPLD */
 264
 265 #define CONFIG_SYS_BR5_PRELIM           0xf8000801
 266 #define CONFIG_SYS_OR5_PRELIM           0xff006e65
 267 #define CONFIG_SYS_EPLD_BASE            0xf8000000
 268 #define CONFIG_SYS_LED_DISP_BASE        0xf8000000
 269 #define CONFIG_SYS_USER_SWITCHES_BASE   0xf8100000
 270 #define CONFIG_SYS_BD_REV               0xf8300000
 271 #define CONFIG_SYS_EEPROM_BASE          0xf8b00000
 272
 273 /*
 274  * SDRAM on the Local Bus (CS3 and CS4)
 275  * Note that most boards have a hardware errata where both the
 276  * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
 277  * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
 278  * A hardware workaround is also available, see README.sbc8548 file.
 279  */
 280 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 281 #define CONFIG_SYS_LBC_SDRAM_SIZE       128             /* LBC SDRAM is 128MB */
 282
 283 /*
 284  * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
 285  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 286  *
 287  * For BR3, need:
 288  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 289  *    port-size = 32-bits = BR2[19:20] = 11
 290  *    no parity checking = BR2[21:22] = 00
 291  *    SDRAM for MSEL = BR2[24:26] = 011
 292  *    Valid = BR[31] = 1
 293  *
 294  * 0    4    8    12   16   20   24   28
 295  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 296  *
 297  */
 298
 299 #define CONFIG_SYS_BR3_PRELIM           0xf0001861
 300
 301 /*
 302  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 303  *
 304  * For OR3, need:
 305  *    64MB mask for AM, OR3[0:7] = 1111 1100
 306  *                 XAM, OR3[17:18] = 11
 307  *    10 columns OR3[19-21] = 011
 308  *    12 rows   OR3[23-25] = 011
 309  *    EAD set for extra time OR[31] = 0
 310  *
 311  * 0    4    8    12   16   20   24   28
 312  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 313  */
 314
 315 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0
 316
 317 /*
 318  * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
 319  * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
 320  *
 321  * For BR4, need:
 322  *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
 323  *    port-size = 32-bits = BR2[19:20] = 11
 324  *    no parity checking = BR2[21:22] = 00
 325  *    SDRAM for MSEL = BR2[24:26] = 011
 326  *    Valid = BR[31] = 1
 327  *
 328  * 0    4    8    12   16   20   24   28
 329  * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
 330  *
 331  */
 332
 333 #define CONFIG_SYS_BR4_PRELIM           0xf4001861
 334
 335 /*
 336  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 337  *
 338  * For OR4, need:
 339  *    64MB mask for AM, OR3[0:7] = 1111 1100
 340  *                 XAM, OR3[17:18] = 11
 341  *    10 columns OR3[19-21] = 011
 342  *    12 rows   OR3[23-25] = 011
 343  *    EAD set for extra time OR[31] = 0
 344  *
 345  * 0    4    8    12   16   20   24   28
 346  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 347  */
 348
 349 #define CONFIG_SYS_OR4_PRELIM           0xfc006cc0
 350
 351 #define CONFIG_SYS_LBC_LCRR             0x00000002    /* LB clock ratio reg */
 352 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 353 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 354 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 355
 356 /*
 357  * Common settings for all Local Bus SDRAM commands.
 358  */
 359 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 360                                 | LSDMR_BSMA1516        \
 361                                 | LSDMR_PRETOACT3       \
 362                                 | LSDMR_ACTTORW3        \
 363                                 | LSDMR_BUFCMD          \
 364                                 | LSDMR_BL8             \
 365                                 | LSDMR_WRC2            \
 366                                 | LSDMR_CL3             \
 367                                 )
 368
 369 #define CONFIG_SYS_LBC_LSDMR_PCHALL     \
 370          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 371 #define CONFIG_SYS_LBC_LSDMR_ARFRSH     \
 372          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 373 #define CONFIG_SYS_LBC_LSDMR_MRW        \
 374          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 375 #define CONFIG_SYS_LBC_LSDMR_RFEN       \
 376          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
 377
 378 #define CONFIG_SYS_INIT_RAM_LOCK        1
 379 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 380 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 381
 382 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 383
 384 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 385 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 386
 387 /*
 388  * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
 389  * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
 390  * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
 391  * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
 392  * thing for MONITOR_LEN in both cases.
 393  */
 394 #define CONFIG_SYS_MONITOR_LEN          (~CONFIG_SYS_TEXT_BASE + 1)
 395 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024) /* Reserved for malloc */
 396
 397 /* Serial Port */
 398 #define CONFIG_CONS_INDEX       1
 399 #define CONFIG_SYS_NS16550_SERIAL
 400 #define CONFIG_SYS_NS16550_REG_SIZE     1
 401 #define CONFIG_SYS_NS16550_CLK          (400000000 / CONFIG_SYS_CLK_DIV)
 402
 403 #define CONFIG_SYS_BAUDRATE_TABLE \
 404         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 405
 406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 407 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 408
 409 /*
 410  * I2C
 411  */
 412 #define CONFIG_SYS_I2C
 413 #define CONFIG_SYS_I2C_FSL
 414 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 415 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 416 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 417 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 418
 419 /*
 420  * General PCI
 421  * Memory space is mapped 1-1, but I/O space must start from 0.
 422  */
 423 #define CONFIG_SYS_PCI_VIRT             0x80000000      /* 1G PCI TLB */
 424 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 425
 426 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 427 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 428 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 429 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 430 #define CONFIG_SYS_PCI1_IO_VIRT         0xe2000000
 431 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 432 #define CONFIG_SYS_PCI1_IO_PHYS         0xe2000000
 433 #define CONFIG_SYS_PCI1_IO_SIZE         0x00800000      /* 8M */
 434
 435 #ifdef CONFIG_PCIE1
 436 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 437 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 438 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 439 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 440 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 441 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 442 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 443 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 444 #endif
 445
 446 #ifdef CONFIG_RIO
 447 /*
 448  * RapidIO MMU
 449  */
 450 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
 451 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 452 #endif
 453
 454 #if defined(CONFIG_PCI)
 455 #undef CONFIG_EEPRO100
 456 #undef CONFIG_TULIP
 457
 458 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 459
 460 #endif  /* CONFIG_PCI */
 461
 462 #if defined(CONFIG_TSEC_ENET)
 463
 464 #define CONFIG_MII              1       /* MII PHY management */
 465 #define CONFIG_TSEC1    1
 466 #define CONFIG_TSEC1_NAME       "eTSEC0"
 467 #define CONFIG_TSEC2    1
 468 #define CONFIG_TSEC2_NAME       "eTSEC1"
 469 #undef CONFIG_MPC85XX_FEC
 470
 471 #define TSEC1_PHY_ADDR          0x19
 472 #define TSEC2_PHY_ADDR          0x1a
 473
 474 #define TSEC1_PHYIDX            0
 475 #define TSEC2_PHYIDX            0
 476
 477 #define TSEC1_FLAGS             TSEC_GIGABIT
 478 #define TSEC2_FLAGS             TSEC_GIGABIT
 479
 480 /* Options are: eTSEC[0-3] */
 481 #define CONFIG_ETHPRIME         "eTSEC0"
 482 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 483 #endif  /* CONFIG_TSEC_ENET */
 484
 485 /*
 486  * Environment
 487  */
 488 #define CONFIG_ENV_SIZE         0x2000
 489 #if CONFIG_SYS_TEXT_BASE == 0xfff00000  /* Boot from 64MB SODIMM */
 490 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x80000)
 491 #define CONFIG_ENV_SECT_SIZE    0x80000 /* 512K(one sector) for env */
 492 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000        /* Boot from 8MB soldered flash */
 493 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 494 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 495 #else
 496 #warning undefined environment size/location.
 497 #endif
 498
 499 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 500 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 501
 502 /*
 503  * BOOTP options
 504  */
 505 #define CONFIG_BOOTP_BOOTFILESIZE
 506 #define CONFIG_BOOTP_BOOTPATH
 507 #define CONFIG_BOOTP_GATEWAY
 508 #define CONFIG_BOOTP_HOSTNAME
 509
 510 /*
 511  * Command line configuration.
 512  */
 513 #define CONFIG_CMD_REGINFO
 514
 515 #if defined(CONFIG_PCI)
 516     #define CONFIG_CMD_PCI
 517 #endif
 518
 519 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 520
 521 /*
 522  * Miscellaneous configurable options
 523  */
 524 #define CONFIG_CMDLINE_EDITING                  /* undef to save memory */
 525 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 526 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 527 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 528 #if defined(CONFIG_CMD_KGDB)
 529 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 530 #else
 531 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 532 #endif
 533 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 534 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 535 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 536
 537 /*
 538  * For booting Linux, the board info and command line data
 539  * have to be in the first 8 MB of memory, since this is
 540  * the maximum mapped by the Linux kernel during initialization.
 541  */
 542 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 543
 544 #if defined(CONFIG_CMD_KGDB)
 545 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 546 #endif
 547
 548 /*
 549  * Environment Configuration
 550  */
 551 #if defined(CONFIG_TSEC_ENET)
 552 #define CONFIG_HAS_ETH0
 553 #define CONFIG_HAS_ETH1
 554 #endif
 555
 556 #define CONFIG_IPADDR    192.168.0.55
 557
 558 #define CONFIG_HOSTNAME  sbc8548
 559 #define CONFIG_ROOTPATH  "/opt/eldk/ppc_85xx"
 560 #define CONFIG_BOOTFILE  "/uImage"
 561 #define CONFIG_UBOOTPATH /u-boot.bin    /* TFTP server */
 562
 563 #define CONFIG_SERVERIP  192.168.0.2
 564 #define CONFIG_GATEWAYIP 192.168.0.1
 565 #define CONFIG_NETMASK   255.255.255.0
 566
 567 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 568
 569 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs*/
 570
 571 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 572 "netdev=eth0\0"                                         \
 573 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                             \
 574 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 575         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 576         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 577         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 578         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 579         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 580 "consoledev=ttyS0\0"                            \
 581 "ramdiskaddr=2000000\0"                 \
 582 "ramdiskfile=uRamdisk\0"                        \
 583 "fdtaddr=1e00000\0"                             \
 584 "fdtfile=sbc8548.dtb\0"
 585
 586 #define CONFIG_NFSBOOTCOMMAND                                           \
 587    "setenv bootargs root=/dev/nfs rw "                                  \
 588       "nfsroot=$serverip:$rootpath "                                    \
 589       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 590       "console=$consoledev,$baudrate $othbootargs;"                     \
 591    "tftp $loadaddr $bootfile;"                                          \
 592    "tftp $fdtaddr $fdtfile;"                                            \
 593    "bootm $loadaddr - $fdtaddr"
 594
 595 #define CONFIG_RAMBOOTCOMMAND \
 596    "setenv bootargs root=/dev/ram rw "                                  \
 597       "console=$consoledev,$baudrate $othbootargs;"                     \
 598    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 599    "tftp $loadaddr $bootfile;"                                          \
 600    "tftp $fdtaddr $fdtfile;"                                            \
 601    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 602
 603 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 604
 605 #endif  /* __CONFIG_H */