include/configs/sbc8548.h

   1 /*
   2  * Copyright 2007,2009 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Copyright 2004, 2007 Freescale Semiconductor.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 /*
  10  * sbc8548 board configuration file
  11  * Please refer to doc/README.sbc8548 for more info.
  12  */
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * Top level Makefile configuration choices
  18  */
  19 #ifdef CONFIG_PCI
  20 #define CONFIG_PCI_INDIRECT_BRIDGE
  21 #define CONFIG_PCI1
  22 #endif
  23
  24 #ifdef CONFIG_66
  25 #define CONFIG_SYS_CLK_DIV 1
  26 #endif
  27
  28 #ifdef CONFIG_33
  29 #define CONFIG_SYS_CLK_DIV 2
  30 #endif
  31
  32 #ifdef CONFIG_PCIE
  33 #define CONFIG_PCIE1
  34 #endif
  35
  36 /*
  37  * High Level Configuration Options
  38  */
  39
  40 /*
  41  * If you want to boot from the SODIMM flash, instead of the soldered
  42  * on flash, set this, and change JP12, SW2:8 accordingly.
  43  */
  44 #undef CONFIG_SYS_ALT_BOOT
  45
  46 #undef CONFIG_RIO
  47
  48 #ifdef CONFIG_PCI
  49 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  50 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  51 #endif
  52 #ifdef CONFIG_PCIE1
  53 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  54 #endif
  55
  56 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  57 #define CONFIG_ENV_OVERWRITE
  58
  59 #define CONFIG_INTERRUPTS               /* enable pci, srio, ddr interrupts */
  60
  61 /*
  62  * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
  63  */
  64 #ifndef CONFIG_SYS_CLK_DIV
  65 #define CONFIG_SYS_CLK_DIV      1       /* 2, if 33MHz PCI card installed */
  66 #endif
  67 #define CONFIG_SYS_CLK_FREQ     (66000000 / CONFIG_SYS_CLK_DIV)
  68
  69 /*
  70  * These can be toggled for performance analysis, otherwise use default.
  71  */
  72 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  73 #define CONFIG_BTB                      /* toggle branch predition */
  74
  75 /*
  76  * Only possible on E500 Version 2 or newer cores.
  77  */
  78 #define CONFIG_ENABLE_36BIT_PHYS        1
  79
  80 #undef  CONFIG_SYS_DRAM_TEST                    /* memory test, takes time */
  81 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  82 #define CONFIG_SYS_MEMTEST_END          0x00400000
  83
  84 #define CONFIG_SYS_CCSRBAR              0xe0000000
  85 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  86
  87 /* DDR Setup */
  88 #undef CONFIG_FSL_DDR_INTERACTIVE
  89 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  90 /*
  91  * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD
  92  * to collide, meaning you couldn't reliably read either. So
  93  * physically remove the LBC PC100 SDRAM module from the board
  94  * before enabling the two SPD options below, or check that you
  95  * have the hardware fix on your board via "i2c probe" and looking
  96  * for a device at 0x53.
  97  */
  98 #undef CONFIG_SPD_EEPROM                /* Use SPD EEPROM for DDR setup */
  99 #undef CONFIG_DDR_SPD
 100
 101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
 102 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 103
 104 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 105 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 106 #define CONFIG_VERY_BIG_RAM
 107
 108 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 109 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 110
 111 /*
 112  * The hardware fix for the I2C address collision puts the DDR
 113  * SPD at 0x53, but if we are running on an older board w/o the
 114  * fix, it will still be at 0x51.  We check 0x53 1st.
 115  */
 116 #define SPD_EEPROM_ADDRESS      0x51    /* CTLR 0 DIMM 0 */
 117 #define ALT_SPD_EEPROM_ADDRESS  0x53    /* CTLR 0 DIMM 0 */
 118
 119 /*
 120  * Make sure required options are set
 121  */
 122 #ifndef CONFIG_SPD_EEPROM
 123         #define CONFIG_SYS_SDRAM_SIZE   256             /* DDR is 256MB */
 124         #define CONFIG_SYS_DDR_CONTROL  0xc300c000
 125 #endif
 126
 127 #undef CONFIG_CLOCKS_IN_MHZ
 128
 129 /*
 130  * FLASH on the Local Bus
 131  * Two banks, one 8MB the other 64MB, using the CFI driver.
 132  * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have
 133  * CS0 the 8MB boot flash, and CS6 the 64MB flash.
 134  *
 135  *      Default:
 136  *      ec00_0000       efff_ffff       64MB SODIMM
 137  *      ff80_0000       ffff_ffff       8MB soldered flash
 138  *
 139  *      Alternate:
 140  *      ef80_0000       efff_ffff       8MB soldered flash
 141  *      fc00_0000       ffff_ffff       64MB SODIMM
 142  *
 143  * BR0_8M:
 144  *    Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
 145  *    Port Size = 8 bits = BRx[19:20] = 01
 146  *    Use GPCM = BRx[24:26] = 000
 147  *    Valid = BRx[31] = 1
 148  *
 149  * BR0_64M:
 150  *    Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0
 151  *    Port Size = 32 bits = BRx[19:20] = 11
 152  *
 153  * 0    4    8    12   16   20   24   28
 154  * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801    BR0_8M
 155  * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801    BR0_64M
 156  */
 157 #define CONFIG_SYS_BR0_8M       0xff800801
 158 #define CONFIG_SYS_BR0_64M      0xfc001801
 159
 160 /*
 161  * BR6_8M:
 162  *    Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0
 163  *    Port Size = 8 bits = BRx[19:20] = 01
 164  *    Use GPCM = BRx[24:26] = 000
 165  *    Valid = BRx[31] = 1
 166
 167  * BR6_64M:
 168  *    Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0
 169  *    Port Size = 32 bits = BRx[19:20] = 11
 170  *
 171  * 0    4    8    12   16   20   24   28
 172  * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801    BR6_8M
 173  * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801    BR6_64M
 174  */
 175 #define CONFIG_SYS_BR6_8M       0xef800801
 176 #define CONFIG_SYS_BR6_64M      0xec001801
 177
 178 /*
 179  * OR0_8M:
 180  *    Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
 181  *    XAM = OR0[17:18] = 11
 182  *    CSNT = OR0[20] = 1
 183  *    ACS = half cycle delay = OR0[21:22] = 11
 184  *    SCY = 6 = OR0[24:27] = 0110
 185  *    TRLX = use relaxed timing = OR0[29] = 1
 186  *    EAD = use external address latch delay = OR0[31] = 1
 187  *
 188  * OR0_64M:
 189  *    Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0
 190  *
 191  *
 192  * 0    4    8    12   16   20   24   28
 193  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR0_8M
 194  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR0_64M
 195  */
 196 #define CONFIG_SYS_OR0_8M       0xff806e65
 197 #define CONFIG_SYS_OR0_64M      0xfc006e65
 198
 199 /*
 200  * OR6_8M:
 201  *    Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0
 202  *    XAM = OR6[17:18] = 11
 203  *    CSNT = OR6[20] = 1
 204  *    ACS = half cycle delay = OR6[21:22] = 11
 205  *    SCY = 6 = OR6[24:27] = 0110
 206  *    TRLX = use relaxed timing = OR6[29] = 1
 207  *    EAD = use external address latch delay = OR6[31] = 1
 208  *
 209  * OR6_64M:
 210  *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
 211  *
 212  * 0    4    8    12   16   20   24   28
 213  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    OR6_8M
 214  * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65    OR6_64M
 215  */
 216 #define CONFIG_SYS_OR6_8M       0xff806e65
 217 #define CONFIG_SYS_OR6_64M      0xfc006e65
 218
 219 #ifndef CONFIG_SYS_ALT_BOOT             /* JP12 in default position */
 220 #define CONFIG_SYS_BOOT_BLOCK           0xff800000      /* start of 8MB Flash */
 221 #define CONFIG_SYS_ALT_FLASH            0xec000000      /* 64MB "user" flash */
 222
 223 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_8M
 224 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_8M
 225
 226 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_64M
 227 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_64M
 228 #else                                   /* JP12 in alternate position */
 229 #define CONFIG_SYS_BOOT_BLOCK           0xfc000000      /* start 64MB Flash */
 230 #define CONFIG_SYS_ALT_FLASH            0xef800000      /* 8MB soldered flash */
 231
 232 #define CONFIG_SYS_BR0_PRELIM           CONFIG_SYS_BR0_64M
 233 #define CONFIG_SYS_OR0_PRELIM           CONFIG_SYS_OR0_64M
 234
 235 #define CONFIG_SYS_BR6_PRELIM           CONFIG_SYS_BR6_8M
 236 #define CONFIG_SYS_OR6_PRELIM           CONFIG_SYS_OR6_8M
 237 #endif
 238
 239 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_BOOT_BLOCK
 240 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, \
 241                                          CONFIG_SYS_ALT_FLASH}
 242 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 243 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* sectors per device */
 244 #undef  CONFIG_SYS_FLASH_CHECKSUM
 245 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 246 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 247
 248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 249
 250 #define CONFIG_FLASH_CFI_DRIVER
 251 #define CONFIG_SYS_FLASH_CFI
 252 #define CONFIG_SYS_FLASH_EMPTY_INFO
 253
 254 /* CS5 = Local bus peripherals controlled by the EPLD */
 255
 256 #define CONFIG_SYS_BR5_PRELIM           0xf8000801
 257 #define CONFIG_SYS_OR5_PRELIM           0xff006e65
 258 #define CONFIG_SYS_EPLD_BASE            0xf8000000
 259 #define CONFIG_SYS_LED_DISP_BASE        0xf8000000
 260 #define CONFIG_SYS_USER_SWITCHES_BASE   0xf8100000
 261 #define CONFIG_SYS_BD_REV               0xf8300000
 262 #define CONFIG_SYS_EEPROM_BASE          0xf8b00000
 263
 264 /*
 265  * SDRAM on the Local Bus (CS3 and CS4)
 266  * Note that most boards have a hardware errata where both the
 267  * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible
 268  * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM.
 269  * A hardware workaround is also available, see README.sbc8548 file.
 270  */
 271 #define CONFIG_SYS_LBC_SDRAM_BASE       0xf0000000      /* Localbus SDRAM */
 272 #define CONFIG_SYS_LBC_SDRAM_SIZE       128             /* LBC SDRAM is 128MB */
 273
 274 /*
 275  * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
 276  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 277  *
 278  * For BR3, need:
 279  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 280  *    port-size = 32-bits = BR2[19:20] = 11
 281  *    no parity checking = BR2[21:22] = 00
 282  *    SDRAM for MSEL = BR2[24:26] = 011
 283  *    Valid = BR[31] = 1
 284  *
 285  * 0    4    8    12   16   20   24   28
 286  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 287  *
 288  */
 289
 290 #define CONFIG_SYS_BR3_PRELIM           0xf0001861
 291
 292 /*
 293  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 294  *
 295  * For OR3, need:
 296  *    64MB mask for AM, OR3[0:7] = 1111 1100
 297  *                 XAM, OR3[17:18] = 11
 298  *    10 columns OR3[19-21] = 011
 299  *    12 rows   OR3[23-25] = 011
 300  *    EAD set for extra time OR[31] = 0
 301  *
 302  * 0    4    8    12   16   20   24   28
 303  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 304  */
 305
 306 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0
 307
 308 /*
 309  * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
 310  * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
 311  *
 312  * For BR4, need:
 313  *    Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
 314  *    port-size = 32-bits = BR2[19:20] = 11
 315  *    no parity checking = BR2[21:22] = 00
 316  *    SDRAM for MSEL = BR2[24:26] = 011
 317  *    Valid = BR[31] = 1
 318  *
 319  * 0    4    8    12   16   20   24   28
 320  * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
 321  *
 322  */
 323
 324 #define CONFIG_SYS_BR4_PRELIM           0xf4001861
 325
 326 /*
 327  * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 328  *
 329  * For OR4, need:
 330  *    64MB mask for AM, OR3[0:7] = 1111 1100
 331  *                 XAM, OR3[17:18] = 11
 332  *    10 columns OR3[19-21] = 011
 333  *    12 rows   OR3[23-25] = 011
 334  *    EAD set for extra time OR[31] = 0
 335  *
 336  * 0    4    8    12   16   20   24   28
 337  * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
 338  */
 339
 340 #define CONFIG_SYS_OR4_PRELIM           0xfc006cc0
 341
 342 #define CONFIG_SYS_LBC_LCRR             0x00000002    /* LB clock ratio reg */
 343 #define CONFIG_SYS_LBC_LBCR             0x00000000    /* LB config reg */
 344 #define CONFIG_SYS_LBC_LSRT             0x20000000  /* LB sdram refresh timer */
 345 #define CONFIG_SYS_LBC_MRTPR            0x00000000  /* LB refresh timer prescal*/
 346
 347 /*
 348  * Common settings for all Local Bus SDRAM commands.
 349  */
 350 #define CONFIG_SYS_LBC_LSDMR_COMMON     ( LSDMR_RFCR16          \
 351                                 | LSDMR_BSMA1516        \
 352                                 | LSDMR_PRETOACT3       \
 353                                 | LSDMR_ACTTORW3        \
 354                                 | LSDMR_BUFCMD          \
 355                                 | LSDMR_BL8             \
 356                                 | LSDMR_WRC2            \
 357                                 | LSDMR_CL3             \
 358                                 )
 359
 360 #define CONFIG_SYS_LBC_LSDMR_PCHALL     \
 361          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 362 #define CONFIG_SYS_LBC_LSDMR_ARFRSH     \
 363          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 364 #define CONFIG_SYS_LBC_LSDMR_MRW        \
 365          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 366 #define CONFIG_SYS_LBC_LSDMR_RFEN       \
 367          (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN)
 368
 369 #define CONFIG_SYS_INIT_RAM_LOCK        1
 370 #define CONFIG_SYS_INIT_RAM_ADDR        0xe4010000      /* Initial RAM address */
 371 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 372
 373 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000      /* relocate boot L2SRAM */
 374
 375 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 376 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 377
 378 /*
 379  * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
 380  * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total).  For SODIMM
 381  * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
 382  * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total).  This dynamically sets the right
 383  * thing for MONITOR_LEN in both cases.
 384  */
 385 #define CONFIG_SYS_MONITOR_LEN          (~CONFIG_SYS_TEXT_BASE + 1)
 386 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024) /* Reserved for malloc */
 387
 388 /* Serial Port */
 389 #define CONFIG_CONS_INDEX       1
 390 #define CONFIG_SYS_NS16550_SERIAL
 391 #define CONFIG_SYS_NS16550_REG_SIZE     1
 392 #define CONFIG_SYS_NS16550_CLK          (400000000 / CONFIG_SYS_CLK_DIV)
 393
 394 #define CONFIG_SYS_BAUDRATE_TABLE \
 395         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 396
 397 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 398 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 399
 400 /*
 401  * I2C
 402  */
 403 #define CONFIG_SYS_I2C
 404 #define CONFIG_SYS_I2C_FSL
 405 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 406 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 407 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 408 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 409
 410 /*
 411  * General PCI
 412  * Memory space is mapped 1-1, but I/O space must start from 0.
 413  */
 414 #define CONFIG_SYS_PCI_VIRT             0x80000000      /* 1G PCI TLB */
 415 #define CONFIG_SYS_PCI_PHYS             0x80000000      /* 1G PCI TLB */
 416
 417 #define CONFIG_SYS_PCI1_MEM_VIRT        0x80000000
 418 #define CONFIG_SYS_PCI1_MEM_BUS         0x80000000
 419 #define CONFIG_SYS_PCI1_MEM_PHYS        0x80000000
 420 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 421 #define CONFIG_SYS_PCI1_IO_VIRT         0xe2000000
 422 #define CONFIG_SYS_PCI1_IO_BUS          0x00000000
 423 #define CONFIG_SYS_PCI1_IO_PHYS         0xe2000000
 424 #define CONFIG_SYS_PCI1_IO_SIZE         0x00800000      /* 8M */
 425
 426 #ifdef CONFIG_PCIE1
 427 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xa0000000
 428 #define CONFIG_SYS_PCIE1_MEM_BUS        0xa0000000
 429 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xa0000000
 430 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 431 #define CONFIG_SYS_PCIE1_IO_VIRT        0xe2800000
 432 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 433 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe2800000
 434 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 435 #endif
 436
 437 #ifdef CONFIG_RIO
 438 /*
 439  * RapidIO MMU
 440  */
 441 #define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
 442 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 512M */
 443 #endif
 444
 445 #if defined(CONFIG_PCI)
 446 #undef CONFIG_EEPRO100
 447 #undef CONFIG_TULIP
 448
 449 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 450
 451 #endif  /* CONFIG_PCI */
 452
 453 #if defined(CONFIG_TSEC_ENET)
 454
 455 #define CONFIG_MII              1       /* MII PHY management */
 456 #define CONFIG_TSEC1    1
 457 #define CONFIG_TSEC1_NAME       "eTSEC0"
 458 #define CONFIG_TSEC2    1
 459 #define CONFIG_TSEC2_NAME       "eTSEC1"
 460 #undef CONFIG_MPC85XX_FEC
 461
 462 #define TSEC1_PHY_ADDR          0x19
 463 #define TSEC2_PHY_ADDR          0x1a
 464
 465 #define TSEC1_PHYIDX            0
 466 #define TSEC2_PHYIDX            0
 467
 468 #define TSEC1_FLAGS             TSEC_GIGABIT
 469 #define TSEC2_FLAGS             TSEC_GIGABIT
 470
 471 /* Options are: eTSEC[0-3] */
 472 #define CONFIG_ETHPRIME         "eTSEC0"
 473 #endif  /* CONFIG_TSEC_ENET */
 474
 475 /*
 476  * Environment
 477  */
 478 #define CONFIG_ENV_SIZE         0x2000
 479 #if CONFIG_SYS_TEXT_BASE == 0xfff00000  /* Boot from 64MB SODIMM */
 480 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x80000)
 481 #define CONFIG_ENV_SECT_SIZE    0x80000 /* 512K(one sector) for env */
 482 #elif CONFIG_SYS_TEXT_BASE == 0xfffa0000        /* Boot from 8MB soldered flash */
 483 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 484 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 485 #else
 486 #warning undefined environment size/location.
 487 #endif
 488
 489 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 490 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 491
 492 /*
 493  * BOOTP options
 494  */
 495 #define CONFIG_BOOTP_BOOTFILESIZE
 496
 497 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 498
 499 /*
 500  * Miscellaneous configurable options
 501  */
 502 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 503
 504 /*
 505  * For booting Linux, the board info and command line data
 506  * have to be in the first 8 MB of memory, since this is
 507  * the maximum mapped by the Linux kernel during initialization.
 508  */
 509 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 510
 511 #if defined(CONFIG_CMD_KGDB)
 512 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 513 #endif
 514
 515 /*
 516  * Environment Configuration
 517  */
 518 #if defined(CONFIG_TSEC_ENET)
 519 #define CONFIG_HAS_ETH0
 520 #define CONFIG_HAS_ETH1
 521 #endif
 522
 523 #define CONFIG_IPADDR    192.168.0.55
 524
 525 #define CONFIG_HOSTNAME  sbc8548
 526 #define CONFIG_ROOTPATH  "/opt/eldk/ppc_85xx"
 527 #define CONFIG_BOOTFILE  "/uImage"
 528 #define CONFIG_UBOOTPATH /u-boot.bin    /* TFTP server */
 529
 530 #define CONFIG_SERVERIP  192.168.0.2
 531 #define CONFIG_GATEWAYIP 192.168.0.1
 532 #define CONFIG_NETMASK   255.255.255.0
 533
 534 #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
 535
 536 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 537 "netdev=eth0\0"                                         \
 538 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                             \
 539 "tftpflash=tftpboot $loadaddr $uboot; "                 \
 540         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 541         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 542         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 543         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 544         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 545 "consoledev=ttyS0\0"                            \
 546 "ramdiskaddr=2000000\0"                 \
 547 "ramdiskfile=uRamdisk\0"                        \
 548 "fdtaddr=1e00000\0"                             \
 549 "fdtfile=sbc8548.dtb\0"
 550
 551 #define CONFIG_NFSBOOTCOMMAND                                           \
 552    "setenv bootargs root=/dev/nfs rw "                                  \
 553       "nfsroot=$serverip:$rootpath "                                    \
 554       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 555       "console=$consoledev,$baudrate $othbootargs;"                     \
 556    "tftp $loadaddr $bootfile;"                                          \
 557    "tftp $fdtaddr $fdtfile;"                                            \
 558    "bootm $loadaddr - $fdtaddr"
 559
 560 #define CONFIG_RAMBOOTCOMMAND \
 561    "setenv bootargs root=/dev/ram rw "                                  \
 562       "console=$consoledev,$baudrate $othbootargs;"                     \
 563    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 564    "tftp $loadaddr $bootfile;"                                          \
 565    "tftp $fdtaddr $fdtfile;"                                            \
 566    "bootm $loadaddr $ramdiskaddr $fdtaddr"
 567
 568 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 569
 570 #endif  /* __CONFIG_H */