include/configs/sbc8560.h

   1 /*
   2  * (C) Copyright 2002,2003 Motorola,Inc.
   3  * Xianghua Xiao <X.Xiao@motorola.com>
   4  *
   5  * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
   6  * Added support for Wind River SBC8560 board
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * sbc8560 board configuration file.
  29  */
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * Top level Makefile configuration choices
  36  */
  37 #ifdef CONFIG_66
  38 #define CONFIG_PCI_66
  39 #endif
  40
  41 /*
  42  * High Level Configuration Options
  43  */
  44 #define CONFIG_BOOKE            1       /* BOOKE                        */
  45 #define CONFIG_E500             1       /* BOOKE e500 family            */
  46 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560              */
  47 #define CONFIG_MPC85xx_REV1     1       /* MPC85xx Rev 1.0 chip         */
  48
  49
  50 #define CONFIG_CPM2             1       /* has CPM2 */
  51 #define CONFIG_SBC8560          1       /* configuration for SBC8560 board */
  52 #define CONFIG_MPC8560          1
  53
  54 /* XXX flagging this as something I might want to delete */
  55 #define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific    */
  56
  57 #define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  58 #undef  CONFIG_PCI                      /* pci ethernet support         */
  59 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support     */
  60
  61 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  62
  63 #define CONFIG_ENV_OVERWRITE
  64
  65 /* Using Localbus SDRAM to emulate flash before we can program the flash,
  66  * normally you need a flash-boot image(u-boot.bin), if so undef this.
  67  */
  68 #undef CONFIG_RAM_AS_FLASH
  69
  70 #if defined(CONFIG_PCI_66)              /* some PCI card is 33Mhz only  */
  71   #define CONFIG_SYS_CLK_FREQ   66000000/* sysclk for MPC85xx           */
  72 #else
  73   #define CONFIG_SYS_CLK_FREQ   33000000/* most pci cards are 33Mhz     */
  74 #endif
  75
  76 /* below can be toggled for performance analysis. otherwise use default */
  77 #define CONFIG_L2_CACHE                     /* toggle L2 cache          */
  78 #undef  CONFIG_BTB                          /* toggle branch predition  */
  79
  80 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
  81 #define CONFIG_RESET_PHY_R      1           /* Call reset_phy()         */
  82
  83 #undef  CONFIG_SYS_DRAM_TEST                        /* memory test, takes time  */
  84 #define CONFIG_SYS_MEMTEST_START        0x00200000  /* memtest region */
  85 #define CONFIG_SYS_MEMTEST_END          0x00400000
  86
  87 #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
  88      defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
  89      defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
  90 #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
  91 #endif
  92
  93 /*
  94  * Base addresses -- Note these are effective addresses where the
  95  * actual resources get mapped (not physical addresses)
  96  */
  97 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default      */
  98
  99 #if XXX
 100   #define CONFIG_SYS_CCSRBAR            0xfdf00000      /* relocated CCSRBAR    */
 101 #else
 102   #define CONFIG_SYS_CCSRBAR            0xff700000      /* default CCSRBAR      */
 103 #endif
 104 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 105 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR    */
 106
 107 #define CONFIG_SYS_SDRAM_SIZE           512             /* DDR is 512MB */
 108
 109 /* DDR Setup */
 110 #define CONFIG_FSL_DDR1
 111 #undef CONFIG_FSL_DDR_INTERACTIVE
 112 #undef  CONFIG_DDR_ECC                          /* only for ECC DDR module      */
 113 #undef  CONFIG_SPD_EEPROM                       /* Use SPD EEPROM for DDR setup */
 114 #undef  CONFIG_DDR_SPD
 115
 116 #if defined(CONFIG_MPC85xx_REV1)
 117   #define CONFIG_DDR_DLL                        /* possible DLL fix needed      */
 118 #endif
 119
 120 #undef  CONFIG_DDR_ECC                      /* only for ECC DDR module */
 121 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
 122 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 123
 124 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 125 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 126 #define CONFIG_VERY_BIG_RAM
 127
 128 #define CONFIG_NUM_DDR_CONTROLLERS      1
 129 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 130 #define CONFIG_CHIP_SELECTS_PER_CTRL    2
 131
 132 /* I2C addresses of SPD EEPROMs */
 133 #define SPD_EEPROM_ADDRESS      0x55    /* CTLR 0 DIMM 0 */
 134
 135 #undef CONFIG_CLOCKS_IN_MHZ
 136
 137 #if defined(CONFIG_RAM_AS_FLASH)
 138   #define CONFIG_SYS_LBC_SDRAM_BASE     0xfc000000      /* Localbus SDRAM */
 139   #define CONFIG_SYS_FLASH_BASE 0xf8000000      /* start of FLASH 8M  */
 140   #define CONFIG_SYS_BR0_PRELIM 0xf8000801      /* port size 8bit */
 141   #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7      /* 8MB Flash            */
 142 #else /* Boot from real Flash */
 143   #define CONFIG_SYS_LBC_SDRAM_BASE     0xf8000000      /* Localbus SDRAM */
 144   #define CONFIG_SYS_FLASH_BASE 0xff800000      /* start of FLASH 8M    */
 145   #define CONFIG_SYS_BR0_PRELIM 0xff800801      /* port size 8bit      */
 146   #define CONFIG_SYS_OR0_PRELIM 0xff800ff7      /* 8MB Flash            */
 147 #endif
 148 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB    */
 149
 150 /* local bus definitions */
 151 #define CONFIG_SYS_BR1_PRELIM           0xe4001801      /* 64M, 32-bit flash */
 152 #define CONFIG_SYS_OR1_PRELIM           0xfc000ff7
 153
 154 #define CONFIG_SYS_BR2_PRELIM           0x00000000      /* CS2 not used */
 155 #define CONFIG_SYS_OR2_PRELIM           0x00000000
 156
 157 #define CONFIG_SYS_BR3_PRELIM           0xf0001861      /* 64MB localbus SDRAM  */
 158 #define CONFIG_SYS_OR3_PRELIM           0xfc000cc1
 159
 160 #if defined(CONFIG_RAM_AS_FLASH)
 161   #define CONFIG_SYS_BR4_PRELIM 0xf4001861      /* 64M localbus SDRAM */
 162 #else
 163   #define CONFIG_SYS_BR4_PRELIM 0xf8001861      /* 64M localbus SDRAM */
 164 #endif
 165 #define CONFIG_SYS_OR4_PRELIM           0xfc000cc1
 166
 167 #define CONFIG_SYS_BR5_PRELIM           0xfc000801      /* 16M CS5 misc devices */
 168 #if 1
 169   #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
 170 #else
 171   #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
 172 #endif
 173
 174 #define CONFIG_SYS_BR6_PRELIM           0xe0001801      /* 64M, 32-bit flash */
 175 #define CONFIG_SYS_OR6_PRELIM           0xfc000ff7
 176 #define CONFIG_SYS_LBC_LCRR             0x00030002      /* local bus freq       */
 177 #define CONFIG_SYS_LBC_LBCR             0x00000000
 178 #define CONFIG_SYS_LBC_LSRT             0x20000000
 179 #define CONFIG_SYS_LBC_MRTPR            0x20000000
 180 #define CONFIG_SYS_LBC_LSDMR_1          0x2861b723
 181 #define CONFIG_SYS_LBC_LSDMR_2          0x0861b723
 182 #define CONFIG_SYS_LBC_LSDMR_3          0x0861b723
 183 #define CONFIG_SYS_LBC_LSDMR_4          0x1861b723
 184 #define CONFIG_SYS_LBC_LSDMR_5          0x4061b723
 185
 186 /* just hijack the MOT BCSR def for SBC8560 misc devices */
 187 #define CONFIG_SYS_BCSR         ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 188 /* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 189
 190 #define CONFIG_SYS_INIT_RAM_LOCK        1
 191 #define CONFIG_SYS_INIT_RAM_ADDR        0x70000000      /* Initial RAM address  */
 192 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 193
 194 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 195 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 196 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 197
 198 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 199 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 200
 201 /* Serial Port */
 202 #undef  CONFIG_CONS_ON_SCC      /* define if console on SCC */
 203 #undef  CONFIG_CONS_NONE        /* define if console on something else */
 204
 205 #define CONFIG_CONS_INDEX       1
 206 #define CONFIG_SYS_NS16550
 207 #define CONFIG_SYS_NS16550_SERIAL
 208 #define CONFIG_SYS_NS16550_REG_SIZE     1
 209 #define CONFIG_SYS_NS16550_CLK          1843200 /* get_bus_freq(0) */
 210 #define CONFIG_BAUDRATE         9600
 211
 212 #define CONFIG_SYS_BAUDRATE_TABLE  \
 213         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 214
 215 #define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
 216 #define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
 217
 218 /* Use the HUSH parser */
 219 #define CONFIG_SYS_HUSH_PARSER
 220 #ifdef  CONFIG_SYS_HUSH_PARSER
 221 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 222 #endif
 223
 224 /* pass open firmware flat tree */
 225 #define CONFIG_OF_LIBFDT                1
 226 #define CONFIG_OF_BOARD_SETUP           1
 227 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 228
 229 /*
 230  * I2C
 231  */
 232 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 233 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 234 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 235 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 236 #define CONFIG_SYS_I2C_SLAVE            0x7F
 237 #define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 238 #define CONFIG_SYS_I2C_OFFSET           0x3000
 239
 240 #define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
 241 #define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
 242 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 243
 244 #ifdef CONFIG_TSEC_ENET
 245
 246 #ifndef CONFIG_NET_MULTI
 247 #define CONFIG_NET_MULTI        1
 248 #endif
 249
 250 #ifndef CONFIG_MII
 251 #define CONFIG_MII              1       /* MII PHY management */
 252 #endif
 253 #define CONFIG_TSEC1    1
 254 #define CONFIG_TSEC1_NAME       "TSEC0"
 255 #define CONFIG_TSEC2    1
 256 #define CONFIG_TSEC2_NAME       "TSEC1"
 257 #define TSEC1_PHY_ADDR          0x19
 258 #define TSEC2_PHY_ADDR          0x1a
 259 #define TSEC1_PHYIDX            0
 260 #define TSEC2_PHYIDX            0
 261 #define TSEC1_FLAGS             TSEC_GIGABIT
 262 #define TSEC2_FLAGS             TSEC_GIGABIT
 263
 264 /* Options are: TSEC[0-1] */
 265 #define CONFIG_ETHPRIME         "TSEC0"
 266
 267 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 268
 269   #undef  CONFIG_ETHER_NONE             /* define if ether on something else */
 270   #define CONFIG_ETHER_ON_FCC2          /* cpm FCC ethernet support     */
 271   #define CONFIG_ETHER_INDEX    2       /* which channel for ether  */
 272
 273   #if (CONFIG_ETHER_INDEX == 2)
 274     /*
 275      * - Rx-CLK is CLK13
 276      * - Tx-CLK is CLK14
 277      * - Select bus for bd/buffers
 278      * - Full duplex
 279      */
 280     #define CONFIG_SYS_CMXFCR_MASK      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 281     #define CONFIG_SYS_CMXFCR_VALUE     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 282     #define CONFIG_SYS_CPMFCR_RAMTYPE   0
 283     #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
 284
 285   #elif (CONFIG_ETHER_INDEX == 3)
 286     /* need more definitions here for FE3 */
 287   #endif                                /* CONFIG_ETHER_INDEX */
 288
 289   #define CONFIG_MII                    /* MII PHY management */
 290   #define CONFIG_BITBANGMII             /* bit-bang MII PHY management  */
 291   /*
 292    * GPIO pins used for bit-banged MII communications
 293    */
 294   #define MDIO_PORT     2               /* Port C */
 295   #define MDIO_DECLARE  volatile ioport_t *iop = ioport_addr ( \
 296                                 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 297   #define MDC_DECLARE   MDIO_DECLARE
 298
 299   #define MDIO_ACTIVE   (iop->pdir |=  0x00400000)
 300   #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
 301   #define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
 302
 303   #define MDIO(bit)     if(bit) iop->pdat |=  0x00400000; \
 304                         else    iop->pdat &= ~0x00400000
 305
 306   #define MDC(bit)      if(bit) iop->pdat |=  0x00200000; \
 307                         else    iop->pdat &= ~0x00200000
 308
 309   #define MIIDELAY      udelay(1)
 310
 311 #endif
 312
 313 /*-----------------------------------------------------------------------
 314  * FLASH and environment organization
 315  */
 316
 317 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant      */
 318 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver        */
 319 #if 0
 320 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)   */
 321 #define CONFIG_SYS_FLASH_PROTECTION             /* use hardware protection      */
 322 #endif
 323 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* max number of sectors on one chip */
 324 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks   */
 325
 326 #undef  CONFIG_SYS_FLASH_CHECKSUM
 327 #define CONFIG_SYS_FLASH_ERASE_TOUT     200000  /* Timeout for Flash Erase (in ms) */
 328 #define CONFIG_SYS_FLASH_WRITE_TOUT     50000   /* Timeout for Flash Write (in ms) */
 329
 330 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor   */
 331
 332 #if 0
 333 /* XXX This doesn't work and I don't want to fix it */
 334 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 335   #define CONFIG_SYS_RAMBOOT
 336 #else
 337   #undef  CONFIG_SYS_RAMBOOT
 338 #endif
 339 #endif
 340
 341 /* Environment */
 342 #if !defined(CONFIG_SYS_RAMBOOT)
 343   #if defined(CONFIG_RAM_AS_FLASH)
 344     #define CONFIG_ENV_IS_NOWHERE
 345     #define CONFIG_ENV_ADDR     (CONFIG_SYS_FLASH_BASE + 0x100000)
 346     #define CONFIG_ENV_SIZE     0x2000
 347   #else
 348     #define CONFIG_ENV_IS_IN_FLASH      1
 349     #define CONFIG_ENV_SECT_SIZE        0x20000 /* 128K(one sector) for env */
 350     #define CONFIG_ENV_ADDR     (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 351     #define CONFIG_ENV_SIZE     0x2000 /* CONFIG_ENV_SECT_SIZE */
 352   #endif
 353 #else
 354   #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now      */
 355   #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only     */
 356   #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 357   #define CONFIG_ENV_SIZE               0x2000
 358 #endif
 359
 360 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
 361 /*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
 362 #define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 363
 364 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 365 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 366
 367
 368 /*
 369  * BOOTP options
 370  */
 371 #define CONFIG_BOOTP_BOOTFILESIZE
 372 #define CONFIG_BOOTP_BOOTPATH
 373 #define CONFIG_BOOTP_GATEWAY
 374 #define CONFIG_BOOTP_HOSTNAME
 375
 376
 377 /*
 378  * Command line configuration.
 379  */
 380 #include <config_cmd_default.h>
 381
 382 #define CONFIG_CMD_PING
 383 #define CONFIG_CMD_I2C
 384 #define CONFIG_CMD_REGINFO
 385
 386 #if defined(CONFIG_PCI)
 387     #define CONFIG_CMD_PCI
 388 #endif
 389
 390 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 391     #define CONFIG_CMD_MII
 392 #endif
 393
 394 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
 395     #undef CONFIG_CMD_SAVEENV
 396     #undef CONFIG_CMD_LOADS
 397 #endif
 398
 399
 400 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 401
 402 /*
 403  * Miscellaneous configurable options
 404  */
 405 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 406 #define CONFIG_SYS_PROMPT       "SBC8560=> " /* Monitor Command Prompt  */
 407 #if defined(CONFIG_CMD_KGDB)
 408   #define CONFIG_SYS_CBSIZE     1024            /* Console I/O Buffer Size      */
 409 #else
 410   #define CONFIG_SYS_CBSIZE     256             /* Console I/O Buffer Size      */
 411 #endif
 412 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 413 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 414 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 415 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 416 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 417
 418 /*
 419  * For booting Linux, the board info and command line data
 420  * have to be in the first 8 MB of memory, since this is
 421  * the maximum mapped by the Linux kernel during initialization.
 422  */
 423 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 424
 425 /*
 426  * Internal Definitions
 427  *
 428  * Boot Flags
 429  */
 430 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 431 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 432
 433 #if defined(CONFIG_CMD_KGDB)
 434 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 435 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 436 #endif
 437
 438 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 439 #define CONFIG_HAS_ETH0
 440 #define CONFIG_HAS_ETH1
 441 #endif
 442
 443 /* You can compile in a MAC address and your custom net settings by using
 444  * the following syntax.  Your board should be marked with the assigned
 445  * MAC addresses directly on it.
 446  *
 447  * #define CONFIG_ETHADDR               de:ad:be:ef:00:00
 448  * #define CONFIG_ETH1ADDR              fa:ke:ad:dr:es:s!
 449  * #define CONFIG_SERVERIP              <server ip>
 450  * #define CONFIG_IPADDR                <board ip>
 451  * #define CONFIG_GATEWAYIP             <gateway ip>
 452  * #define CONFIG_NETMASK               <your netmask>
 453  */
 454
 455 #define CONFIG_HOSTNAME         SBC8560
 456 #define CONFIG_ROOTPATH         /home/ppc
 457 #define CONFIG_BOOTFILE         uImage
 458
 459 #define CONFIG_EXTRA_ENV_SETTINGS               \
 460         "netdev=eth0\0"                         \
 461         "consoledev=ttyS0\0"                            \
 462         "ramdiskaddr=2000000\0"                 \
 463         "ramdiskfile=ramdisk.uboot\0"                   \
 464         "fdtaddr=c00000\0"                              \
 465         "fdtfile=sbc8560.dtb\0"
 466
 467 #define CONFIG_NFSBOOTCOMMAND                                           \
 468         "setenv bootargs root=/dev/nfs rw "                             \
 469                 "nfsroot=$serverip:$rootpath "                          \
 470                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 471                 "console=$consoledev,$baudrate $othbootargs;"           \
 472         "tftp $loadaddr $bootfile;"                                     \
 473         "tftp $fdtaddr $fdtfile;"                                       \
 474         "bootm $loadaddr - $fdtaddr"
 475
 476
 477 #define CONFIG_RAMBOOTCOMMAND \
 478         "setenv bootargs root=/dev/ram rw "                             \
 479                 "console=$consoledev,$baudrate $othbootargs;"           \
 480         "tftp $ramdiskaddr $ramdiskfile;"                               \
 481         "tftp $loadaddr $bootfile;"                                     \
 482         "tftp $fdtaddr $fdtfile;"                                       \
 483         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 484
 485 #define CONFIG_BOOTCOMMAND      CONFIG_NFSBOOTCOMMAND
 486
 487 #endif  /* __CONFIG_H */