include/configs/sbc8641d.h

   1 /*
   2  * Copyright 2007 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Joe Hamman <joe.hamman@embeddedspecialties.com>
   5  *
   6  * Copyright 2006 Freescale Semiconductor.
   7  *
   8  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 /*
  14  * SBC8641D board configuration file
  15  *
  16  * Make sure you change the MAC address and other network params first,
  17  * search for CONFIG_SERVERIP, etc in this file.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /* High Level Configuration Options */
  24 #define CONFIG_MP               1       /* support multiple processors */
  25 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  26
  27 #ifdef RUN_DIAG
  28 #define CONFIG_SYS_DIAG_ADDR        0xff800000
  29 #endif
  30
  31 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100
  32
  33 /*
  34  * virtual address to be used for temporary mappings.  There
  35  * should be 128k free at this VA.
  36  */
  37 #define CONFIG_SYS_SCRATCH_VA   0xe8000000
  38
  39 #define CONFIG_SYS_SRIO
  40 #define CONFIG_SRIO1                    /* SRIO port 1 */
  41
  42 #define CONFIG_PCIE1            1       /* PCIE controller 1 (slot 1) */
  43 #define CONFIG_PCIE2            1       /* PCIE controller 2 (slot 2) */
  44 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  45 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  46
  47 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  48 #define CONFIG_ENV_OVERWRITE
  49
  50 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  51 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  52
  53 #undef CONFIG_SPD_EEPROM                /* Do not use SPD EEPROM for DDR setup*/
  54 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  55 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  56 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  57 #define CACHE_LINE_INTERLEAVING         0x20000000
  58 #define PAGE_INTERLEAVING               0x21000000
  59 #define BANK_INTERLEAVING               0x22000000
  60 #define SUPER_BANK_INTERLEAVING         0x23000000
  61
  62 #define CONFIG_ALTIVEC          1
  63
  64 /*
  65  * L2CR setup -- make sure this is right for your board!
  66  */
  67 #define CONFIG_SYS_L2
  68 #define L2_INIT         0
  69 #define L2_ENABLE       (L2CR_L2E)
  70
  71 #ifndef CONFIG_SYS_CLK_FREQ
  72 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  73 #endif
  74
  75 #undef  CONFIG_SYS_DRAM_TEST                            /* memory test, takes time */
  76 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  77 #define CONFIG_SYS_MEMTEST_END          0x00400000
  78
  79 /*
  80  * Base addresses -- Note these are effective addresses where the
  81  * actual resources get mapped (not physical addresses)
  82  */
  83 #define CONFIG_SYS_CCSRBAR              0xf8000000      /* relocated CCSRBAR */
  84 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
  85
  86 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  87 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
  88 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
  89
  90 /*
  91  * DDR Setup
  92  */
  93 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory */
  94 #define CONFIG_SYS_DDR_SDRAM_BASE2      0x10000000      /* DDR bank 2 */
  95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  96 #define CONFIG_SYS_SDRAM_BASE2          CONFIG_SYS_DDR_SDRAM_BASE2
  97 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
  98 #define CONFIG_VERY_BIG_RAM
  99
 100 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 101 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 102
 103 #if defined(CONFIG_SPD_EEPROM)
 104     /*
 105      * Determine DDR configuration from I2C interface.
 106      */
 107     #define SPD_EEPROM_ADDRESS1         0x51            /* DDR DIMM */
 108     #define SPD_EEPROM_ADDRESS2         0x52            /* DDR DIMM */
 109     #define SPD_EEPROM_ADDRESS3         0x53            /* DDR DIMM */
 110     #define SPD_EEPROM_ADDRESS4         0x54            /* DDR DIMM */
 111
 112 #else
 113     /*
 114      * Manually set up DDR1 & DDR2 parameters
 115      */
 116
 117     #define CONFIG_SYS_SDRAM_SIZE       512             /* DDR is 512MB */
 118
 119     #define CONFIG_SYS_DDR_CS0_BNDS     0x0000000F
 120     #define CONFIG_SYS_DDR_CS1_BNDS     0x00000000
 121     #define CONFIG_SYS_DDR_CS2_BNDS     0x00000000
 122     #define CONFIG_SYS_DDR_CS3_BNDS     0x00000000
 123     #define CONFIG_SYS_DDR_CS0_CONFIG   0x80010102
 124     #define CONFIG_SYS_DDR_CS1_CONFIG   0x00000000
 125     #define CONFIG_SYS_DDR_CS2_CONFIG   0x00000000
 126     #define CONFIG_SYS_DDR_CS3_CONFIG   0x00000000
 127     #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 128     #define CONFIG_SYS_DDR_TIMING_0     0x00220802
 129     #define CONFIG_SYS_DDR_TIMING_1     0x38377322
 130     #define CONFIG_SYS_DDR_TIMING_2     0x002040c7
 131     #define CONFIG_SYS_DDR_CFG_1A       0x43008008
 132     #define CONFIG_SYS_DDR_CFG_2        0x24401000
 133     #define CONFIG_SYS_DDR_MODE_1       0x23c00542
 134     #define CONFIG_SYS_DDR_MODE_2       0x00000000
 135     #define CONFIG_SYS_DDR_MODE_CTL     0x00000000
 136     #define CONFIG_SYS_DDR_INTERVAL     0x05080100
 137     #define CONFIG_SYS_DDR_DATA_INIT    0x00000000
 138     #define CONFIG_SYS_DDR_CLK_CTRL     0x03800000
 139     #define CONFIG_SYS_DDR_CFG_1B       0xC3008008
 140
 141     #define CONFIG_SYS_DDR2_CS0_BNDS    0x0010001F
 142     #define CONFIG_SYS_DDR2_CS1_BNDS    0x00000000
 143     #define CONFIG_SYS_DDR2_CS2_BNDS    0x00000000
 144     #define CONFIG_SYS_DDR2_CS3_BNDS    0x00000000
 145     #define CONFIG_SYS_DDR2_CS0_CONFIG  0x80010102
 146     #define CONFIG_SYS_DDR2_CS1_CONFIG  0x00000000
 147     #define CONFIG_SYS_DDR2_CS2_CONFIG  0x00000000
 148     #define CONFIG_SYS_DDR2_CS3_CONFIG  0x00000000
 149     #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
 150     #define CONFIG_SYS_DDR2_TIMING_0    0x00220802
 151     #define CONFIG_SYS_DDR2_TIMING_1    0x38377322
 152     #define CONFIG_SYS_DDR2_TIMING_2    0x002040c7
 153     #define CONFIG_SYS_DDR2_CFG_1A      0x43008008
 154     #define CONFIG_SYS_DDR2_CFG_2       0x24401000
 155     #define CONFIG_SYS_DDR2_MODE_1      0x23c00542
 156     #define CONFIG_SYS_DDR2_MODE_2      0x00000000
 157     #define CONFIG_SYS_DDR2_MODE_CTL    0x00000000
 158     #define CONFIG_SYS_DDR2_INTERVAL    0x05080100
 159     #define CONFIG_SYS_DDR2_DATA_INIT   0x00000000
 160     #define CONFIG_SYS_DDR2_CLK_CTRL    0x03800000
 161     #define CONFIG_SYS_DDR2_CFG_1B      0xC3008008
 162
 163 #endif
 164
 165 /* #define CONFIG_ID_EEPROM     1
 166 #define ID_EEPROM_ADDR 0x57 */
 167
 168 /*
 169  * The SBC8641D contains 16MB flash space at ff000000.
 170  */
 171 #define CONFIG_SYS_FLASH_BASE      0xff000000  /* start of FLASH 16M */
 172
 173 /* Flash */
 174 #define CONFIG_SYS_BR0_PRELIM           0xff001001      /* port size 16bit */
 175 #define CONFIG_SYS_OR0_PRELIM           0xff006e65      /* 16MB Boot Flash area */
 176
 177 /* 64KB EEPROM */
 178 #define CONFIG_SYS_BR1_PRELIM           0xf0000801      /* port size 16bit */
 179 #define CONFIG_SYS_OR1_PRELIM           0xffff6e65      /* 64K EEPROM area */
 180
 181 /* EPLD - User switches, board id, LEDs */
 182 #define CONFIG_SYS_BR2_PRELIM           0xf1000801      /* port size 16bit */
 183 #define CONFIG_SYS_OR2_PRELIM           0xfff06e65      /* EPLD (switches, board ID, LEDs) area */
 184
 185 /* Local bus SDRAM 128MB */
 186 #define CONFIG_SYS_BR3_PRELIM           0xe0001861      /* port size ?bit */
 187 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0      /* 128MB local bus SDRAM area (1st half) */
 188 #define CONFIG_SYS_BR4_PRELIM           0xe4001861      /* port size ?bit */
 189 #define CONFIG_SYS_OR4_PRELIM           0xfc006cc0      /* 128MB local bus SDRAM area (2nd half) */
 190
 191 /* Disk on Chip (DOC) 128MB */
 192 #define CONFIG_SYS_BR5_PRELIM           0xe8001001      /* port size ?bit */
 193 #define CONFIG_SYS_OR5_PRELIM           0xf8006e65      /* 128MB local bus SDRAM area (2nd half) */
 194
 195 /* LCD */
 196 #define CONFIG_SYS_BR6_PRELIM           0xf4000801      /* port size ?bit */
 197 #define CONFIG_SYS_OR6_PRELIM           0xfff06e65      /* 128MB local bus SDRAM area (2nd half) */
 198
 199 /* Control logic & misc peripherals */
 200 #define CONFIG_SYS_BR7_PRELIM           0xf2000801      /* port size ?bit */
 201 #define CONFIG_SYS_OR7_PRELIM           0xfff06e65      /* 128MB local bus SDRAM area (2nd half) */
 202
 203 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 204 #define CONFIG_SYS_MAX_FLASH_SECT       131             /* sectors per device */
 205
 206 #undef  CONFIG_SYS_FLASH_CHECKSUM
 207 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 208 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 209 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 210 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 211
 212 #define CONFIG_FLASH_CFI_DRIVER
 213 #define CONFIG_SYS_FLASH_CFI
 214 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 215 #define CONFIG_SYS_FLASH_EMPTY_INFO
 216 #define CONFIG_SYS_FLASH_PROTECTION
 217
 218 #undef CONFIG_CLOCKS_IN_MHZ
 219
 220 #define CONFIG_SYS_INIT_RAM_LOCK        1
 221 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 222 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 223 #else
 224 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 225 #endif
 226 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 227
 228 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 229 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 230
 231 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384 kB for Mon */
 232 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 233
 234 /* Serial Port */
 235 #define CONFIG_CONS_INDEX     1
 236 #define CONFIG_SYS_NS16550_SERIAL
 237 #define CONFIG_SYS_NS16550_REG_SIZE    1
 238 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 239
 240 #define CONFIG_SYS_BAUDRATE_TABLE  \
 241         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 242
 243 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 244 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 245
 246 /*
 247  * I2C
 248  */
 249 #define CONFIG_SYS_I2C
 250 #define CONFIG_SYS_I2C_FSL
 251 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 252 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 253 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3100
 254 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 255
 256 /*
 257  * RapidIO MMU
 258  */
 259 #define CONFIG_SYS_SRIO1_MEM_BASE       0xc0000000      /* base address */
 260 #define CONFIG_SYS_SRIO1_MEM_PHYS       CONFIG_SYS_SRIO1_MEM_BASE
 261 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 262
 263 /*
 264  * General PCI
 265  * Addresses are mapped 1-1.
 266  */
 267 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 268 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 269 #define CONFIG_SYS_PCIE1_MEM_VIRT       CONFIG_SYS_PCIE1_MEM_BUS
 270 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 271 #define CONFIG_SYS_PCIE1_IO_BUS         0xe2000000
 272 #define CONFIG_SYS_PCIE1_IO_PHYS        CONFIG_SYS_PCIE1_IO_BUS
 273 #define CONFIG_SYS_PCIE1_IO_VIRT        CONFIG_SYS_PCIE1_IO_BUS
 274 #define CONFIG_SYS_PCIE1_IO_SIZE        0x1000000       /* 16M */
 275
 276 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 277 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 278 #define CONFIG_SYS_PCIE2_MEM_VIRT       CONFIG_SYS_PCIE2_MEM_BUS
 279 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 280 #define CONFIG_SYS_PCIE2_IO_BUS         0xe3000000
 281 #define CONFIG_SYS_PCIE2_IO_PHYS        CONFIG_SYS_PCIE2_IO_BUS
 282 #define CONFIG_SYS_PCIE2_IO_VIRT        CONFIG_SYS_PCIE2_IO_BUS
 283 #define CONFIG_SYS_PCIE2_IO_SIZE        0x1000000       /* 16M */
 284
 285 #if defined(CONFIG_PCI)
 286
 287 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 288
 289 #undef CONFIG_EEPRO100
 290 #undef CONFIG_TULIP
 291
 292 #if !defined(CONFIG_PCI_PNP)
 293     #define PCI_ENET0_IOADDR    0xe0000000
 294     #define PCI_ENET0_MEMADDR   0xe0000000
 295     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 296 #endif
 297
 298 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 299
 300 #ifdef CONFIG_SCSI_AHCI
 301 #define CONFIG_SATA_ULI5288
 302 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 303 #define CONFIG_SYS_SCSI_MAX_LUN 1
 304 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 305 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 306 #endif
 307
 308 #endif  /* CONFIG_PCI */
 309
 310 #if defined(CONFIG_TSEC_ENET)
 311
 312 /* #define CONFIG_MII           1 */    /* MII PHY management */
 313
 314 #define CONFIG_TSEC1    1
 315 #define CONFIG_TSEC1_NAME       "eTSEC1"
 316 #define CONFIG_TSEC2    1
 317 #define CONFIG_TSEC2_NAME       "eTSEC2"
 318 #define CONFIG_TSEC3    1
 319 #define CONFIG_TSEC3_NAME       "eTSEC3"
 320 #define CONFIG_TSEC4    1
 321 #define CONFIG_TSEC4_NAME       "eTSEC4"
 322
 323 #define TSEC1_PHY_ADDR          0x1F
 324 #define TSEC2_PHY_ADDR          0x00
 325 #define TSEC3_PHY_ADDR          0x01
 326 #define TSEC4_PHY_ADDR          0x02
 327 #define TSEC1_PHYIDX            0
 328 #define TSEC2_PHYIDX            0
 329 #define TSEC3_PHYIDX            0
 330 #define TSEC4_PHYIDX            0
 331 #define TSEC1_FLAGS             TSEC_GIGABIT
 332 #define TSEC2_FLAGS             TSEC_GIGABIT
 333 #define TSEC3_FLAGS             TSEC_GIGABIT
 334 #define TSEC4_FLAGS             TSEC_GIGABIT
 335
 336 #define CONFIG_SYS_TBIPA_VALUE  0x1e    /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
 337
 338 #define CONFIG_ETHPRIME         "eTSEC1"
 339
 340 #endif  /* CONFIG_TSEC_ENET */
 341
 342 /*
 343  * BAT0         2G     Cacheable, non-guarded
 344  * 0x0000_0000  2G     DDR
 345  */
 346 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 347 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 348 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 349 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 350
 351 /*
 352  * BAT1         1G     Cache-inhibited, guarded
 353  * 0x8000_0000  512M   PCI-Express 1 Memory
 354  * 0xa000_0000  512M   PCI-Express 2 Memory
 355  *      Changed it for operating from 0xd0000000
 356  */
 357 #define CONFIG_SYS_DBAT1L       ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
 358                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 359 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
 360 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 361 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 362
 363 /*
 364  * BAT2         512M   Cache-inhibited, guarded
 365  * 0xc000_0000  512M   RapidIO Memory
 366  */
 367 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
 368                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 369 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
 370 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 371 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 372
 373 /*
 374  * BAT3         4M     Cache-inhibited, guarded
 375  * 0xf800_0000  4M     CCSR
 376  */
 377 #define CONFIG_SYS_DBAT3L       ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
 378                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 379 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 380 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 381 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 382
 383 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 384 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 385                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 386                                        | BATL_GUARDEDSTORAGE)
 387 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 388                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 389 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 390                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 391 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 392 #endif
 393
 394 /*
 395  * BAT4         32M    Cache-inhibited, guarded
 396  * 0xe200_0000  16M    PCI-Express 1 I/O
 397  * 0xe300_0000  16M    PCI-Express 2 I/0
 398  *    Note that this is at 0xe0000000
 399  */
 400 #define CONFIG_SYS_DBAT4L       ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
 401                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 402 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
 403 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 404 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 405
 406 /*
 407  * BAT5         128K   Cacheable, non-guarded
 408  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
 409  */
 410 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 411 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 412 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 413 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 414
 415 /*
 416  * BAT6         32M    Cache-inhibited, guarded
 417  * 0xfe00_0000  32M    FLASH
 418  */
 419 #define CONFIG_SYS_DBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 420                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 421 #define CONFIG_SYS_DBAT6U       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
 422 #define CONFIG_SYS_IBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 423 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 424
 425 /* Map the last 1M of flash where we're running from reset */
 426 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 427                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 428 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 429 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 430                                  | BATL_MEMCOHERENCE)
 431 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 432
 433 #define CONFIG_SYS_DBAT7L       0x00000000
 434 #define CONFIG_SYS_DBAT7U       0x00000000
 435 #define CONFIG_SYS_IBAT7L       0x00000000
 436 #define CONFIG_SYS_IBAT7U       0x00000000
 437
 438 /*
 439  * Environment
 440  */
 441 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 442 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128k(one sector) for env */
 443 #define CONFIG_ENV_SIZE         0x2000
 444
 445 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 446 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 447
 448 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 449
 450 /*
 451  * Miscellaneous configurable options
 452  */
 453 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 454
 455 /*
 456  * For booting Linux, the board info and command line data
 457  * have to be in the first 8 MB of memory, since this is
 458  * the maximum mapped by the Linux kernel during initialization.
 459  */
 460 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 461
 462 /* Cache Configuration */
 463 #define CONFIG_SYS_DCACHE_SIZE          32768
 464 #define CONFIG_SYS_CACHELINE_SIZE       32
 465 #if defined(CONFIG_CMD_KGDB)
 466 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 467 #endif
 468
 469 #if defined(CONFIG_CMD_KGDB)
 470 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 471 #endif
 472
 473 /*
 474  * Environment Configuration
 475  */
 476
 477 #define CONFIG_HAS_ETH0         1
 478 #define CONFIG_HAS_ETH1         1
 479 #define CONFIG_HAS_ETH2         1
 480 #define CONFIG_HAS_ETH3         1
 481
 482 #define CONFIG_IPADDR           192.168.0.50
 483
 484 #define CONFIG_HOSTNAME         sbc8641d
 485 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_74xx"
 486 #define CONFIG_BOOTFILE         "uImage"
 487
 488 #define CONFIG_SERVERIP         192.168.0.2
 489 #define CONFIG_GATEWAYIP        192.168.0.1
 490 #define CONFIG_NETMASK          255.255.255.0
 491
 492 /* default location for tftp and bootm */
 493 #define CONFIG_LOADADDR         1000000
 494
 495 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 496    "netdev=eth0\0"                                                      \
 497    "consoledev=ttyS0\0"                                                 \
 498    "ramdiskaddr=2000000\0"                                              \
 499    "ramdiskfile=uRamdisk\0"                                             \
 500    "dtbaddr=400000\0"                                                   \
 501    "dtbfile=sbc8641d.dtb\0"                                             \
 502    "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0"     \
 503    "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0"    \
 504    "maxcpus=1"
 505
 506 #define CONFIG_NFSBOOTCOMMAND                                           \
 507    "setenv bootargs root=/dev/nfs rw "                                  \
 508       "nfsroot=$serverip:$rootpath "                                    \
 509       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 510       "console=$consoledev,$baudrate $othbootargs;"                     \
 511    "tftp $loadaddr $bootfile;"                                          \
 512    "tftp $dtbaddr $dtbfile;"                                            \
 513    "bootm $loadaddr - $dtbaddr"
 514
 515 #define CONFIG_RAMBOOTCOMMAND                                           \
 516    "setenv bootargs root=/dev/ram rw "                                  \
 517       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 518       "console=$consoledev,$baudrate $othbootargs;"                     \
 519    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 520    "tftp $loadaddr $bootfile;"                                          \
 521    "tftp $dtbaddr $dtbfile;"                                            \
 522    "bootm $loadaddr $ramdiskaddr $dtbaddr"
 523
 524 #define CONFIG_FLASHBOOTCOMMAND                                         \
 525    "setenv bootargs root=/dev/ram rw "                                  \
 526       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 527       "console=$consoledev,$baudrate $othbootargs;"                     \
 528    "bootm ffd00000 ffb00000 ffa00000"
 529
 530 #define CONFIG_BOOTCOMMAND  CONFIG_FLASHBOOTCOMMAND
 531
 532 #endif  /* __CONFIG_H */