include/configs/sbc8641d.h

   1 /*
   2  * Copyright 2007 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Joe Hamman <joe.hamman@embeddedspecialties.com>
   5  *
   6  * Copyright 2006 Freescale Semiconductor.
   7  *
   8  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * SBC8641D board configuration file
  31  *
  32  * Make sure you change the MAC address and other network params first,
  33  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_MPC86xx          1       /* MPC86xx */
  41 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  42 #define CONFIG_SBC8641D         1       /* SBC8641D board specific */
  43 #define CONFIG_MP               1       /* support multiple processors */
  44 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  45
  46 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  47
  48 #ifdef RUN_DIAG
  49 #define CONFIG_SYS_DIAG_ADDR        0xff800000
  50 #endif
  51
  52 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100
  53
  54 /*
  55  * virtual address to be used for temporary mappings.  There
  56  * should be 128k free at this VA.
  57  */
  58 #define CONFIG_SYS_SCRATCH_VA   0xe8000000
  59
  60 #define CONFIG_SYS_SRIO
  61 #define CONFIG_SRIO1                    /* SRIO port 1 */
  62
  63 #define CONFIG_PCI              1       /* Enable PCIE */
  64 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  65 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  66 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  67 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  68
  69 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  70 #define CONFIG_ENV_OVERWRITE
  71
  72 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  73 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  74
  75 #undef CONFIG_SPD_EEPROM                /* Do not use SPD EEPROM for DDR setup*/
  76 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  77 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  78 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  79 #define CONFIG_NUM_DDR_CONTROLLERS     2
  80 #define CACHE_LINE_INTERLEAVING         0x20000000
  81 #define PAGE_INTERLEAVING               0x21000000
  82 #define BANK_INTERLEAVING               0x22000000
  83 #define SUPER_BANK_INTERLEAVING         0x23000000
  84
  85
  86 #define CONFIG_ALTIVEC          1
  87
  88 /*
  89  * L2CR setup -- make sure this is right for your board!
  90  */
  91 #define CONFIG_SYS_L2
  92 #define L2_INIT         0
  93 #define L2_ENABLE       (L2CR_L2E)
  94
  95 #ifndef CONFIG_SYS_CLK_FREQ
  96 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  97 #endif
  98
  99 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
 100
 101 #undef  CONFIG_SYS_DRAM_TEST                            /* memory test, takes time */
 102 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
 103 #define CONFIG_SYS_MEMTEST_END          0x00400000
 104
 105 /*
 106  * Base addresses -- Note these are effective addresses where the
 107  * actual resources get mapped (not physical addresses)
 108  */
 109 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 110 #define CONFIG_SYS_CCSRBAR              0xf8000000      /* relocated CCSRBAR */
 111 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 112
 113 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 114 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
 115 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
 116
 117 /*
 118  * DDR Setup
 119  */
 120 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory */
 121 #define CONFIG_SYS_DDR_SDRAM_BASE2      0x10000000      /* DDR bank 2 */
 122 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 123 #define CONFIG_SYS_SDRAM_BASE2          CONFIG_SYS_DDR_SDRAM_BASE2
 124 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 125 #define CONFIG_VERY_BIG_RAM
 126
 127 #define CONFIG_NUM_DDR_CONTROLLERS      2
 128 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 129 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 130
 131 #if defined(CONFIG_SPD_EEPROM)
 132     /*
 133      * Determine DDR configuration from I2C interface.
 134      */
 135     #define SPD_EEPROM_ADDRESS1         0x51            /* DDR DIMM */
 136     #define SPD_EEPROM_ADDRESS2         0x52            /* DDR DIMM */
 137     #define SPD_EEPROM_ADDRESS3         0x53            /* DDR DIMM */
 138     #define SPD_EEPROM_ADDRESS4         0x54            /* DDR DIMM */
 139
 140 #else
 141     /*
 142      * Manually set up DDR1 & DDR2 parameters
 143      */
 144
 145     #define CONFIG_SYS_SDRAM_SIZE       512             /* DDR is 512MB */
 146
 147     #define CONFIG_SYS_DDR_CS0_BNDS     0x0000000F
 148     #define CONFIG_SYS_DDR_CS1_BNDS     0x00000000
 149     #define CONFIG_SYS_DDR_CS2_BNDS     0x00000000
 150     #define CONFIG_SYS_DDR_CS3_BNDS     0x00000000
 151     #define CONFIG_SYS_DDR_CS0_CONFIG   0x80010102
 152     #define CONFIG_SYS_DDR_CS1_CONFIG   0x00000000
 153     #define CONFIG_SYS_DDR_CS2_CONFIG   0x00000000
 154     #define CONFIG_SYS_DDR_CS3_CONFIG   0x00000000
 155     #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 156     #define CONFIG_SYS_DDR_TIMING_0     0x00220802
 157     #define CONFIG_SYS_DDR_TIMING_1     0x38377322
 158     #define CONFIG_SYS_DDR_TIMING_2     0x002040c7
 159     #define CONFIG_SYS_DDR_CFG_1A       0x43008008
 160     #define CONFIG_SYS_DDR_CFG_2        0x24401000
 161     #define CONFIG_SYS_DDR_MODE_1       0x23c00542
 162     #define CONFIG_SYS_DDR_MODE_2       0x00000000
 163     #define CONFIG_SYS_DDR_MODE_CTL     0x00000000
 164     #define CONFIG_SYS_DDR_INTERVAL     0x05080100
 165     #define CONFIG_SYS_DDR_DATA_INIT    0x00000000
 166     #define CONFIG_SYS_DDR_CLK_CTRL     0x03800000
 167     #define CONFIG_SYS_DDR_CFG_1B       0xC3008008
 168
 169     #define CONFIG_SYS_DDR2_CS0_BNDS    0x0010001F
 170     #define CONFIG_SYS_DDR2_CS1_BNDS    0x00000000
 171     #define CONFIG_SYS_DDR2_CS2_BNDS    0x00000000
 172     #define CONFIG_SYS_DDR2_CS3_BNDS    0x00000000
 173     #define CONFIG_SYS_DDR2_CS0_CONFIG  0x80010102
 174     #define CONFIG_SYS_DDR2_CS1_CONFIG  0x00000000
 175     #define CONFIG_SYS_DDR2_CS2_CONFIG  0x00000000
 176     #define CONFIG_SYS_DDR2_CS3_CONFIG  0x00000000
 177     #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
 178     #define CONFIG_SYS_DDR2_TIMING_0    0x00220802
 179     #define CONFIG_SYS_DDR2_TIMING_1    0x38377322
 180     #define CONFIG_SYS_DDR2_TIMING_2    0x002040c7
 181     #define CONFIG_SYS_DDR2_CFG_1A      0x43008008
 182     #define CONFIG_SYS_DDR2_CFG_2       0x24401000
 183     #define CONFIG_SYS_DDR2_MODE_1      0x23c00542
 184     #define CONFIG_SYS_DDR2_MODE_2      0x00000000
 185     #define CONFIG_SYS_DDR2_MODE_CTL    0x00000000
 186     #define CONFIG_SYS_DDR2_INTERVAL    0x05080100
 187     #define CONFIG_SYS_DDR2_DATA_INIT   0x00000000
 188     #define CONFIG_SYS_DDR2_CLK_CTRL    0x03800000
 189     #define CONFIG_SYS_DDR2_CFG_1B      0xC3008008
 190
 191
 192 #endif
 193
 194 /* #define CONFIG_ID_EEPROM     1
 195 #define ID_EEPROM_ADDR 0x57 */
 196
 197 /*
 198  * The SBC8641D contains 16MB flash space at ff000000.
 199  */
 200 #define CONFIG_SYS_FLASH_BASE      0xff000000  /* start of FLASH 16M */
 201
 202 /* Flash */
 203 #define CONFIG_SYS_BR0_PRELIM           0xff001001      /* port size 16bit */
 204 #define CONFIG_SYS_OR0_PRELIM           0xff006e65      /* 16MB Boot Flash area */
 205
 206 /* 64KB EEPROM */
 207 #define CONFIG_SYS_BR1_PRELIM           0xf0000801      /* port size 16bit */
 208 #define CONFIG_SYS_OR1_PRELIM           0xffff6e65      /* 64K EEPROM area */
 209
 210 /* EPLD - User switches, board id, LEDs */
 211 #define CONFIG_SYS_BR2_PRELIM           0xf1000801      /* port size 16bit */
 212 #define CONFIG_SYS_OR2_PRELIM           0xfff06e65      /* EPLD (switches, board ID, LEDs) area */
 213
 214 /* Local bus SDRAM 128MB */
 215 #define CONFIG_SYS_BR3_PRELIM           0xe0001861      /* port size ?bit */
 216 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0      /* 128MB local bus SDRAM area (1st half) */
 217 #define CONFIG_SYS_BR4_PRELIM           0xe4001861      /* port size ?bit */
 218 #define CONFIG_SYS_OR4_PRELIM           0xfc006cc0      /* 128MB local bus SDRAM area (2nd half) */
 219
 220 /* Disk on Chip (DOC) 128MB */
 221 #define CONFIG_SYS_BR5_PRELIM           0xe8001001      /* port size ?bit */
 222 #define CONFIG_SYS_OR5_PRELIM           0xf8006e65      /* 128MB local bus SDRAM area (2nd half) */
 223
 224 /* LCD */
 225 #define CONFIG_SYS_BR6_PRELIM           0xf4000801      /* port size ?bit */
 226 #define CONFIG_SYS_OR6_PRELIM           0xfff06e65      /* 128MB local bus SDRAM area (2nd half) */
 227
 228 /* Control logic & misc peripherals */
 229 #define CONFIG_SYS_BR7_PRELIM           0xf2000801      /* port size ?bit */
 230 #define CONFIG_SYS_OR7_PRELIM           0xfff06e65      /* 128MB local bus SDRAM area (2nd half) */
 231
 232 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 233 #define CONFIG_SYS_MAX_FLASH_SECT       131             /* sectors per device */
 234
 235 #undef  CONFIG_SYS_FLASH_CHECKSUM
 236 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 237 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 238 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 239 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 240
 241 #define CONFIG_FLASH_CFI_DRIVER
 242 #define CONFIG_SYS_FLASH_CFI
 243 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 244 #define CONFIG_SYS_FLASH_EMPTY_INFO
 245 #define CONFIG_SYS_FLASH_PROTECTION
 246
 247 #undef CONFIG_CLOCKS_IN_MHZ
 248
 249 #define CONFIG_SYS_INIT_RAM_LOCK        1
 250 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 251 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 252 #else
 253 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 254 #endif
 255 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 256
 257 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 258 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 259
 260 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 261 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 262
 263 /* Serial Port */
 264 #define CONFIG_CONS_INDEX     1
 265 #define CONFIG_SYS_NS16550
 266 #define CONFIG_SYS_NS16550_SERIAL
 267 #define CONFIG_SYS_NS16550_REG_SIZE    1
 268 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 269
 270 #define CONFIG_SYS_BAUDRATE_TABLE  \
 271         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 272
 273 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 274 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 275
 276 /* Use the HUSH parser */
 277 #define CONFIG_SYS_HUSH_PARSER
 278 #ifdef  CONFIG_SYS_HUSH_PARSER
 279 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 280 #endif
 281
 282 /*
 283  * Pass open firmware flat tree to kernel
 284  */
 285 #define CONFIG_OF_LIBFDT                1
 286 #define CONFIG_OF_BOARD_SETUP           1
 287 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 288
 289 /*
 290  * I2C
 291  */
 292 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 293 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 294 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 295 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 296 #define CONFIG_SYS_I2C_SLAVE            0x7F
 297 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 298 #define CONFIG_SYS_I2C_OFFSET           0x3100
 299
 300 /*
 301  * RapidIO MMU
 302  */
 303 #define CONFIG_SYS_SRIO1_MEM_BASE       0xc0000000      /* base address */
 304 #define CONFIG_SYS_SRIO1_MEM_PHYS       CONFIG_SYS_SRIO1_MEM_BASE
 305 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x20000000      /* 128M */
 306
 307 /*
 308  * General PCI
 309  * Addresses are mapped 1-1.
 310  */
 311 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 312 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 313 #define CONFIG_SYS_PCIE1_MEM_VIRT       CONFIG_SYS_PCIE1_MEM_BUS
 314 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 315 #define CONFIG_SYS_PCIE1_IO_BUS         0xe2000000
 316 #define CONFIG_SYS_PCIE1_IO_PHYS        CONFIG_SYS_PCIE1_IO_BUS
 317 #define CONFIG_SYS_PCIE1_IO_VIRT        CONFIG_SYS_PCIE1_IO_BUS
 318 #define CONFIG_SYS_PCIE1_IO_SIZE        0x1000000       /* 16M */
 319
 320 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 321 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 322 #define CONFIG_SYS_PCIE2_MEM_VIRT       CONFIG_SYS_PCIE2_MEM_BUS
 323 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 324 #define CONFIG_SYS_PCIE2_IO_BUS         0xe3000000
 325 #define CONFIG_SYS_PCIE2_IO_PHYS        CONFIG_SYS_PCIE2_IO_BUS
 326 #define CONFIG_SYS_PCIE2_IO_VIRT        CONFIG_SYS_PCIE2_IO_BUS
 327 #define CONFIG_SYS_PCIE2_IO_SIZE        0x1000000       /* 16M */
 328
 329 #if defined(CONFIG_PCI)
 330
 331 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 332
 333 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 334
 335 #define CONFIG_NET_MULTI
 336 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 337
 338 #undef CONFIG_EEPRO100
 339 #undef CONFIG_TULIP
 340
 341 #if !defined(CONFIG_PCI_PNP)
 342     #define PCI_ENET0_IOADDR    0xe0000000
 343     #define PCI_ENET0_MEMADDR   0xe0000000
 344     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 345 #endif
 346
 347 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 348
 349 #define CONFIG_DOS_PARTITION
 350 #undef CONFIG_SCSI_AHCI
 351
 352 #ifdef CONFIG_SCSI_AHCI
 353 #define CONFIG_SATA_ULI5288
 354 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 355 #define CONFIG_SYS_SCSI_MAX_LUN 1
 356 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 357 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 358 #endif
 359
 360 #endif  /* CONFIG_PCI */
 361
 362 #if defined(CONFIG_TSEC_ENET)
 363
 364 #ifndef CONFIG_NET_MULTI
 365 #define CONFIG_NET_MULTI        1
 366 #endif
 367
 368 /* #define CONFIG_MII           1 */    /* MII PHY management */
 369
 370 #define CONFIG_TSEC1    1
 371 #define CONFIG_TSEC1_NAME       "eTSEC1"
 372 #define CONFIG_TSEC2    1
 373 #define CONFIG_TSEC2_NAME       "eTSEC2"
 374 #define CONFIG_TSEC3    1
 375 #define CONFIG_TSEC3_NAME       "eTSEC3"
 376 #define CONFIG_TSEC4    1
 377 #define CONFIG_TSEC4_NAME       "eTSEC4"
 378
 379 #define TSEC1_PHY_ADDR          0x1F
 380 #define TSEC2_PHY_ADDR          0x00
 381 #define TSEC3_PHY_ADDR          0x01
 382 #define TSEC4_PHY_ADDR          0x02
 383 #define TSEC1_PHYIDX            0
 384 #define TSEC2_PHYIDX            0
 385 #define TSEC3_PHYIDX            0
 386 #define TSEC4_PHYIDX            0
 387 #define TSEC1_FLAGS             TSEC_GIGABIT
 388 #define TSEC2_FLAGS             TSEC_GIGABIT
 389 #define TSEC3_FLAGS             TSEC_GIGABIT
 390 #define TSEC4_FLAGS             TSEC_GIGABIT
 391
 392 #define CONFIG_SYS_TBIPA_VALUE  0x1e    /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
 393
 394 #define CONFIG_ETHPRIME         "eTSEC1"
 395
 396 #endif  /* CONFIG_TSEC_ENET */
 397
 398 /*
 399  * BAT0         2G     Cacheable, non-guarded
 400  * 0x0000_0000  2G     DDR
 401  */
 402 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 403 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 404 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 405 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 406
 407 /*
 408  * BAT1         1G     Cache-inhibited, guarded
 409  * 0x8000_0000  512M   PCI-Express 1 Memory
 410  * 0xa000_0000  512M   PCI-Express 2 Memory
 411  *      Changed it for operating from 0xd0000000
 412  */
 413 #define CONFIG_SYS_DBAT1L       ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
 414                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 415 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
 416 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 417 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 418
 419 /*
 420  * BAT2         512M   Cache-inhibited, guarded
 421  * 0xc000_0000  512M   RapidIO Memory
 422  */
 423 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
 424                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 425 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
 426 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 427 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 428
 429 /*
 430  * BAT3         4M     Cache-inhibited, guarded
 431  * 0xf800_0000  4M     CCSR
 432  */
 433 #define CONFIG_SYS_DBAT3L       ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
 434                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 435 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 436 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 437 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 438
 439 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 440 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 441                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 442                                        | BATL_GUARDEDSTORAGE)
 443 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 444                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 445 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 446                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 447 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 448 #endif
 449
 450 /*
 451  * BAT4         32M    Cache-inhibited, guarded
 452  * 0xe200_0000  16M    PCI-Express 1 I/O
 453  * 0xe300_0000  16M    PCI-Express 2 I/0
 454  *    Note that this is at 0xe0000000
 455  */
 456 #define CONFIG_SYS_DBAT4L       ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
 457                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 458 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
 459 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 460 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 461
 462 /*
 463  * BAT5         128K   Cacheable, non-guarded
 464  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
 465  */
 466 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 467 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 468 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 469 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 470
 471 /*
 472  * BAT6         32M    Cache-inhibited, guarded
 473  * 0xfe00_0000  32M    FLASH
 474  */
 475 #define CONFIG_SYS_DBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 476                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 477 #define CONFIG_SYS_DBAT6U       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
 478 #define CONFIG_SYS_IBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 479 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 480
 481 /* Map the last 1M of flash where we're running from reset */
 482 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 483                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 484 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 485 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 486                                  | BATL_MEMCOHERENCE)
 487 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 488
 489 #define CONFIG_SYS_DBAT7L       0x00000000
 490 #define CONFIG_SYS_DBAT7U       0x00000000
 491 #define CONFIG_SYS_IBAT7L       0x00000000
 492 #define CONFIG_SYS_IBAT7U       0x00000000
 493
 494 /*
 495  * Environment
 496  */
 497 #define CONFIG_ENV_IS_IN_FLASH  1
 498 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 499 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 500 #define CONFIG_ENV_SIZE         0x2000
 501
 502 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 503 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 504
 505 #include <config_cmd_default.h>
 506     #define CONFIG_CMD_PING
 507     #define CONFIG_CMD_I2C
 508     #define CONFIG_CMD_REGINFO
 509
 510 #if defined(CONFIG_PCI)
 511     #define CONFIG_CMD_PCI
 512 #endif
 513
 514 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 515
 516 /*
 517  * Miscellaneous configurable options
 518  */
 519 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 520 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 521 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 522
 523 #if defined(CONFIG_CMD_KGDB)
 524     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 525 #else
 526     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 527 #endif
 528
 529 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 530 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 531 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 532 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 533
 534 /*
 535  * For booting Linux, the board info and command line data
 536  * have to be in the first 8 MB of memory, since this is
 537  * the maximum mapped by the Linux kernel during initialization.
 538  */
 539 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 540
 541 /* Cache Configuration */
 542 #define CONFIG_SYS_DCACHE_SIZE          32768
 543 #define CONFIG_SYS_CACHELINE_SIZE       32
 544 #if defined(CONFIG_CMD_KGDB)
 545 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 546 #endif
 547
 548 #if defined(CONFIG_CMD_KGDB)
 549 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 550 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 551 #endif
 552
 553 /*
 554  * Environment Configuration
 555  */
 556
 557 /* The mac addresses for all ethernet interface */
 558 #if defined(CONFIG_TSEC_ENET)
 559 #define CONFIG_ETHADDR   02:E0:0C:00:00:01
 560 #define CONFIG_ETH1ADDR  02:E0:0C:00:01:FD
 561 #define CONFIG_ETH2ADDR  02:E0:0C:00:02:FD
 562 #define CONFIG_ETH3ADDR  02:E0:0C:00:03:FD
 563 #endif
 564
 565 #define CONFIG_HAS_ETH0         1
 566 #define CONFIG_HAS_ETH1         1
 567 #define CONFIG_HAS_ETH2         1
 568 #define CONFIG_HAS_ETH3         1
 569
 570 #define CONFIG_IPADDR           192.168.0.50
 571
 572 #define CONFIG_HOSTNAME         sbc8641d
 573 #define CONFIG_ROOTPATH         /opt/eldk/ppc_74xx
 574 #define CONFIG_BOOTFILE         uImage
 575
 576 #define CONFIG_SERVERIP         192.168.0.2
 577 #define CONFIG_GATEWAYIP        192.168.0.1
 578 #define CONFIG_NETMASK          255.255.255.0
 579
 580 /* default location for tftp and bootm */
 581 #define CONFIG_LOADADDR         1000000
 582
 583 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 584 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 585
 586 #define CONFIG_BAUDRATE 115200
 587
 588 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 589    "netdev=eth0\0"                                                      \
 590    "consoledev=ttyS0\0"                                                 \
 591    "ramdiskaddr=2000000\0"                                              \
 592    "ramdiskfile=uRamdisk\0"                                             \
 593    "dtbaddr=400000\0"                                                   \
 594    "dtbfile=sbc8641d.dtb\0"                                             \
 595    "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0"     \
 596    "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0"    \
 597    "maxcpus=1"
 598
 599 #define CONFIG_NFSBOOTCOMMAND                                           \
 600    "setenv bootargs root=/dev/nfs rw "                                  \
 601       "nfsroot=$serverip:$rootpath "                                    \
 602       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 603       "console=$consoledev,$baudrate $othbootargs;"                     \
 604    "tftp $loadaddr $bootfile;"                                          \
 605    "tftp $dtbaddr $dtbfile;"                                            \
 606    "bootm $loadaddr - $dtbaddr"
 607
 608 #define CONFIG_RAMBOOTCOMMAND                                           \
 609    "setenv bootargs root=/dev/ram rw "                                  \
 610       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 611       "console=$consoledev,$baudrate $othbootargs;"                     \
 612    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 613    "tftp $loadaddr $bootfile;"                                          \
 614    "tftp $dtbaddr $dtbfile;"                                            \
 615    "bootm $loadaddr $ramdiskaddr $dtbaddr"
 616
 617 #define CONFIG_FLASHBOOTCOMMAND                                         \
 618    "setenv bootargs root=/dev/ram rw "                                  \
 619       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 620       "console=$consoledev,$baudrate $othbootargs;"                     \
 621    "bootm ffd00000 ffb00000 ffa00000"
 622
 623 #define CONFIG_BOOTCOMMAND  CONFIG_FLASHBOOTCOMMAND
 624
 625 #endif  /* __CONFIG_H */