include/configs/sbc8641d.h

   1 /*
   2  * Copyright 2007 Wind River Systems <www.windriver.com>
   3  * Copyright 2007 Embedded Specialties, Inc.
   4  * Joe Hamman <joe.hamman@embeddedspecialties.com>
   5  *
   6  * Copyright 2006 Freescale Semiconductor.
   7  *
   8  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /*
  30  * SBC8641D board configuration file
  31  *
  32  * Make sure you change the MAC address and other network params first,
  33  * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /* High Level Configuration Options */
  40 #define CONFIG_MPC86xx          1       /* MPC86xx */
  41 #define CONFIG_MPC8641          1       /* MPC8641 specific */
  42 #define CONFIG_SBC8641D         1       /* SBC8641D board specific */
  43 #define CONFIG_MP               1       /* support multiple processors */
  44 #define CONFIG_LINUX_RESET_VEC  0x100   /* Reset vector used by Linux */
  45
  46 #ifdef RUN_DIAG
  47 #define CONFIG_SYS_DIAG_ADDR        0xff800000
  48 #endif
  49
  50 #define CONFIG_SYS_RESET_ADDRESS    0xfff00100
  51
  52 /*
  53  * virtual address to be used for temporary mappings.  There
  54  * should be 128k free at this VA.
  55  */
  56 #define CONFIG_SYS_SCRATCH_VA   0xe8000000
  57
  58 #define CONFIG_PCI              1       /* Enable PCIE */
  59 #define CONFIG_PCIE1            1       /* PCIE controler 1 (slot 1) */
  60 #define CONFIG_PCIE2            1       /* PCIE controler 2 (slot 2) */
  61 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  62 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  63
  64 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #define CONFIG_BAT_RW           1       /* Use common BAT rw code */
  68 #define CONFIG_HIGH_BATS        1       /* High BATs supported and enabled */
  69
  70 #undef CONFIG_SPD_EEPROM                /* Do not use SPD EEPROM for DDR setup*/
  71 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  72 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
  73 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
  74 #define CONFIG_NUM_DDR_CONTROLLERS     2
  75 #define CACHE_LINE_INTERLEAVING         0x20000000
  76 #define PAGE_INTERLEAVING               0x21000000
  77 #define BANK_INTERLEAVING               0x22000000
  78 #define SUPER_BANK_INTERLEAVING         0x23000000
  79
  80
  81 #define CONFIG_ALTIVEC          1
  82
  83 /*
  84  * L2CR setup -- make sure this is right for your board!
  85  */
  86 #define CONFIG_SYS_L2
  87 #define L2_INIT         0
  88 #define L2_ENABLE       (L2CR_L2E)
  89
  90 #ifndef CONFIG_SYS_CLK_FREQ
  91 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  92 #endif
  93
  94 #define CONFIG_BOARD_EARLY_INIT_F       1       /* Call board_pre_init */
  95
  96 #undef  CONFIG_SYS_DRAM_TEST                            /* memory test, takes time */
  97 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  98 #define CONFIG_SYS_MEMTEST_END          0x00400000
  99
 100 /*
 101  * Base addresses -- Note these are effective addresses where the
 102  * actual resources get mapped (not physical addresses)
 103  */
 104 #define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default */
 105 #define CONFIG_SYS_CCSRBAR              0xf8000000      /* relocated CCSRBAR */
 106 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR */
 107
 108 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 109 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0x0
 110 #define CONFIG_SYS_CCSRBAR_PHYS         CONFIG_SYS_CCSRBAR_PHYS_LOW
 111
 112 /*
 113  * DDR Setup
 114  */
 115 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory */
 116 #define CONFIG_SYS_DDR_SDRAM_BASE2      0x10000000      /* DDR bank 2 */
 117 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 118 #define CONFIG_SYS_SDRAM_BASE2          CONFIG_SYS_DDR_SDRAM_BASE2
 119 #define CONFIG_SYS_MAX_DDR_BAT_SIZE     0x80000000      /* BAT mapping size */
 120 #define CONFIG_VERY_BIG_RAM
 121
 122 #define CONFIG_NUM_DDR_CONTROLLERS      2
 123 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 124 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 125
 126 #if defined(CONFIG_SPD_EEPROM)
 127     /*
 128      * Determine DDR configuration from I2C interface.
 129      */
 130     #define SPD_EEPROM_ADDRESS1         0x51            /* DDR DIMM */
 131     #define SPD_EEPROM_ADDRESS2         0x52            /* DDR DIMM */
 132     #define SPD_EEPROM_ADDRESS3         0x53            /* DDR DIMM */
 133     #define SPD_EEPROM_ADDRESS4         0x54            /* DDR DIMM */
 134
 135 #else
 136     /*
 137      * Manually set up DDR1 & DDR2 parameters
 138      */
 139
 140     #define CONFIG_SYS_SDRAM_SIZE       512             /* DDR is 512MB */
 141
 142     #define CONFIG_SYS_DDR_CS0_BNDS     0x0000000F
 143     #define CONFIG_SYS_DDR_CS1_BNDS     0x00000000
 144     #define CONFIG_SYS_DDR_CS2_BNDS     0x00000000
 145     #define CONFIG_SYS_DDR_CS3_BNDS     0x00000000
 146     #define CONFIG_SYS_DDR_CS0_CONFIG   0x80010102
 147     #define CONFIG_SYS_DDR_CS1_CONFIG   0x00000000
 148     #define CONFIG_SYS_DDR_CS2_CONFIG   0x00000000
 149     #define CONFIG_SYS_DDR_CS3_CONFIG   0x00000000
 150     #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 151     #define CONFIG_SYS_DDR_TIMING_0     0x00220802
 152     #define CONFIG_SYS_DDR_TIMING_1     0x38377322
 153     #define CONFIG_SYS_DDR_TIMING_2     0x002040c7
 154     #define CONFIG_SYS_DDR_CFG_1A       0x43008008
 155     #define CONFIG_SYS_DDR_CFG_2        0x24401000
 156     #define CONFIG_SYS_DDR_MODE_1       0x23c00542
 157     #define CONFIG_SYS_DDR_MODE_2       0x00000000
 158     #define CONFIG_SYS_DDR_MODE_CTL     0x00000000
 159     #define CONFIG_SYS_DDR_INTERVAL     0x05080100
 160     #define CONFIG_SYS_DDR_DATA_INIT    0x00000000
 161     #define CONFIG_SYS_DDR_CLK_CTRL     0x03800000
 162     #define CONFIG_SYS_DDR_CFG_1B       0xC3008008
 163
 164     #define CONFIG_SYS_DDR2_CS0_BNDS    0x0010001F
 165     #define CONFIG_SYS_DDR2_CS1_BNDS    0x00000000
 166     #define CONFIG_SYS_DDR2_CS2_BNDS    0x00000000
 167     #define CONFIG_SYS_DDR2_CS3_BNDS    0x00000000
 168     #define CONFIG_SYS_DDR2_CS0_CONFIG  0x80010102
 169     #define CONFIG_SYS_DDR2_CS1_CONFIG  0x00000000
 170     #define CONFIG_SYS_DDR2_CS2_CONFIG  0x00000000
 171     #define CONFIG_SYS_DDR2_CS3_CONFIG  0x00000000
 172     #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
 173     #define CONFIG_SYS_DDR2_TIMING_0    0x00220802
 174     #define CONFIG_SYS_DDR2_TIMING_1    0x38377322
 175     #define CONFIG_SYS_DDR2_TIMING_2    0x002040c7
 176     #define CONFIG_SYS_DDR2_CFG_1A      0x43008008
 177     #define CONFIG_SYS_DDR2_CFG_2       0x24401000
 178     #define CONFIG_SYS_DDR2_MODE_1      0x23c00542
 179     #define CONFIG_SYS_DDR2_MODE_2      0x00000000
 180     #define CONFIG_SYS_DDR2_MODE_CTL    0x00000000
 181     #define CONFIG_SYS_DDR2_INTERVAL    0x05080100
 182     #define CONFIG_SYS_DDR2_DATA_INIT   0x00000000
 183     #define CONFIG_SYS_DDR2_CLK_CTRL    0x03800000
 184     #define CONFIG_SYS_DDR2_CFG_1B      0xC3008008
 185
 186
 187 #endif
 188
 189 /* #define CONFIG_ID_EEPROM     1
 190 #define ID_EEPROM_ADDR 0x57 */
 191
 192 /*
 193  * The SBC8641D contains 16MB flash space at ff000000.
 194  */
 195 #define CONFIG_SYS_FLASH_BASE      0xff000000  /* start of FLASH 16M */
 196
 197 /* Flash */
 198 #define CONFIG_SYS_BR0_PRELIM           0xff001001      /* port size 16bit */
 199 #define CONFIG_SYS_OR0_PRELIM           0xff006e65      /* 16MB Boot Flash area */
 200
 201 /* 64KB EEPROM */
 202 #define CONFIG_SYS_BR1_PRELIM           0xf0000801      /* port size 16bit */
 203 #define CONFIG_SYS_OR1_PRELIM           0xffff6e65      /* 64K EEPROM area */
 204
 205 /* EPLD - User switches, board id, LEDs */
 206 #define CONFIG_SYS_BR2_PRELIM           0xf1000801      /* port size 16bit */
 207 #define CONFIG_SYS_OR2_PRELIM           0xfff06e65      /* EPLD (switches, board ID, LEDs) area */
 208
 209 /* Local bus SDRAM 128MB */
 210 #define CONFIG_SYS_BR3_PRELIM           0xe0001861      /* port size ?bit */
 211 #define CONFIG_SYS_OR3_PRELIM           0xfc006cc0      /* 128MB local bus SDRAM area (1st half) */
 212 #define CONFIG_SYS_BR4_PRELIM           0xe4001861      /* port size ?bit */
 213 #define CONFIG_SYS_OR4_PRELIM           0xfc006cc0      /* 128MB local bus SDRAM area (2nd half) */
 214
 215 /* Disk on Chip (DOC) 128MB */
 216 #define CONFIG_SYS_BR5_PRELIM           0xe8001001      /* port size ?bit */
 217 #define CONFIG_SYS_OR5_PRELIM           0xf8006e65      /* 128MB local bus SDRAM area (2nd half) */
 218
 219 /* LCD */
 220 #define CONFIG_SYS_BR6_PRELIM           0xf4000801      /* port size ?bit */
 221 #define CONFIG_SYS_OR6_PRELIM           0xfff06e65      /* 128MB local bus SDRAM area (2nd half) */
 222
 223 /* Control logic & misc peripherals */
 224 #define CONFIG_SYS_BR7_PRELIM           0xf2000801      /* port size ?bit */
 225 #define CONFIG_SYS_OR7_PRELIM           0xfff06e65      /* 128MB local bus SDRAM area (2nd half) */
 226
 227 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 228 #define CONFIG_SYS_MAX_FLASH_SECT       131             /* sectors per device */
 229
 230 #undef  CONFIG_SYS_FLASH_CHECKSUM
 231 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 232 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 233 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE       /* start of monitor */
 234 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000      /* early monitor loc */
 235
 236 #define CONFIG_FLASH_CFI_DRIVER
 237 #define CONFIG_SYS_FLASH_CFI
 238 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 239 #define CONFIG_SYS_FLASH_EMPTY_INFO
 240 #define CONFIG_SYS_FLASH_PROTECTION
 241
 242 #undef CONFIG_CLOCKS_IN_MHZ
 243
 244 #define CONFIG_SYS_INIT_RAM_LOCK        1
 245 #ifndef CONFIG_SYS_INIT_RAM_LOCK
 246 #define CONFIG_SYS_INIT_RAM_ADDR        0x0fd00000      /* Initial RAM address */
 247 #else
 248 #define CONFIG_SYS_INIT_RAM_ADDR        0xf8400000      /* Initial RAM address */
 249 #endif
 250 #define CONFIG_SYS_INIT_RAM_END 0x4000          /* End of used area in RAM */
 251
 252 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 253 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 254 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 255
 256 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 257 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 258
 259 /* Serial Port */
 260 #define CONFIG_CONS_INDEX     1
 261 #define CONFIG_SYS_NS16550
 262 #define CONFIG_SYS_NS16550_SERIAL
 263 #define CONFIG_SYS_NS16550_REG_SIZE    1
 264 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 265
 266 #define CONFIG_SYS_BAUDRATE_TABLE  \
 267         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 268
 269 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
 270 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
 271
 272 /* Use the HUSH parser */
 273 #define CONFIG_SYS_HUSH_PARSER
 274 #ifdef  CONFIG_SYS_HUSH_PARSER
 275 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 276 #endif
 277
 278 /*
 279  * Pass open firmware flat tree to kernel
 280  */
 281 #define CONFIG_OF_LIBFDT                1
 282 #define CONFIG_OF_BOARD_SETUP           1
 283 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 284
 285 /*
 286  * I2C
 287  */
 288 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 289 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 290 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 291 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 292 #define CONFIG_SYS_I2C_SLAVE            0x7F
 293 #define CONFIG_SYS_I2C_NOPROBES        {0x69}   /* Don't probe these addrs */
 294 #define CONFIG_SYS_I2C_OFFSET           0x3100
 295
 296 /*
 297  * RapidIO MMU
 298  */
 299 #define CONFIG_SYS_RIO_MEM_BASE 0xc0000000      /* base address */
 300 #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
 301 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000      /* 128M */
 302
 303 /*
 304  * General PCI
 305  * Addresses are mapped 1-1.
 306  */
 307 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 308 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 309 #define CONFIG_SYS_PCIE1_MEM_VIRT       CONFIG_SYS_PCIE1_MEM_BUS
 310 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 311 #define CONFIG_SYS_PCIE1_IO_BUS         0xe2000000
 312 #define CONFIG_SYS_PCIE1_IO_PHYS        CONFIG_SYS_PCIE1_IO_BUS
 313 #define CONFIG_SYS_PCIE1_IO_VIRT        CONFIG_SYS_PCIE1_IO_BUS
 314 #define CONFIG_SYS_PCIE1_IO_SIZE        0x1000000       /* 16M */
 315
 316 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 317 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
 318 #define CONFIG_SYS_PCIE2_MEM_VIRT       CONFIG_SYS_PCIE2_MEM_BUS
 319 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
 320 #define CONFIG_SYS_PCIE2_IO_BUS         0xe3000000
 321 #define CONFIG_SYS_PCIE2_IO_PHYS        CONFIG_SYS_PCIE2_IO_BUS
 322 #define CONFIG_SYS_PCIE2_IO_VIRT        CONFIG_SYS_PCIE2_IO_BUS
 323 #define CONFIG_SYS_PCIE2_IO_SIZE        0x1000000       /* 16M */
 324
 325 #if defined(CONFIG_PCI)
 326
 327 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 328
 329 #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 330
 331 #define CONFIG_NET_MULTI
 332 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 333
 334 #undef CONFIG_EEPRO100
 335 #undef CONFIG_TULIP
 336
 337 #if !defined(CONFIG_PCI_PNP)
 338     #define PCI_ENET0_IOADDR    0xe0000000
 339     #define PCI_ENET0_MEMADDR   0xe0000000
 340     #define PCI_IDSEL_NUMBER    0x0c    /* slot0->3(IDSEL)=12->15 */
 341 #endif
 342
 343 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 344
 345 #define CONFIG_DOS_PARTITION
 346 #undef CONFIG_SCSI_AHCI
 347
 348 #ifdef CONFIG_SCSI_AHCI
 349 #define CONFIG_SATA_ULI5288
 350 #define CONFIG_SYS_SCSI_MAX_SCSI_ID     4
 351 #define CONFIG_SYS_SCSI_MAX_LUN 1
 352 #define CONFIG_SYS_SCSI_MAX_DEVICE      (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
 353 #define CONFIG_SYS_SCSI_MAXDEVICE       CONFIG_SYS_SCSI_MAX_DEVICE
 354 #endif
 355
 356 #endif  /* CONFIG_PCI */
 357
 358 #if defined(CONFIG_TSEC_ENET)
 359
 360 #ifndef CONFIG_NET_MULTI
 361 #define CONFIG_NET_MULTI        1
 362 #endif
 363
 364 /* #define CONFIG_MII           1 */    /* MII PHY management */
 365
 366 #define CONFIG_TSEC1    1
 367 #define CONFIG_TSEC1_NAME       "eTSEC1"
 368 #define CONFIG_TSEC2    1
 369 #define CONFIG_TSEC2_NAME       "eTSEC2"
 370 #define CONFIG_TSEC3    1
 371 #define CONFIG_TSEC3_NAME       "eTSEC3"
 372 #define CONFIG_TSEC4    1
 373 #define CONFIG_TSEC4_NAME       "eTSEC4"
 374
 375 #define TSEC1_PHY_ADDR          0x1F
 376 #define TSEC2_PHY_ADDR          0x00
 377 #define TSEC3_PHY_ADDR          0x01
 378 #define TSEC4_PHY_ADDR          0x02
 379 #define TSEC1_PHYIDX            0
 380 #define TSEC2_PHYIDX            0
 381 #define TSEC3_PHYIDX            0
 382 #define TSEC4_PHYIDX            0
 383 #define TSEC1_FLAGS             TSEC_GIGABIT
 384 #define TSEC2_FLAGS             TSEC_GIGABIT
 385 #define TSEC3_FLAGS             TSEC_GIGABIT
 386 #define TSEC4_FLAGS             TSEC_GIGABIT
 387
 388 #define CONFIG_SYS_TBIPA_VALUE  0x1e    /* Set TBI address not to conflict with TSEC1_PHY_ADDR */
 389
 390 #define CONFIG_ETHPRIME         "eTSEC1"
 391
 392 #endif  /* CONFIG_TSEC_ENET */
 393
 394 /*
 395  * BAT0         2G     Cacheable, non-guarded
 396  * 0x0000_0000  2G     DDR
 397  */
 398 #define CONFIG_SYS_DBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE)
 399 #define CONFIG_SYS_DBAT0U       (BATU_BL_2G | BATU_VS | BATU_VP)
 400 #define CONFIG_SYS_IBAT0L       (BATL_PP_RW | BATL_MEMCOHERENCE )
 401 #define CONFIG_SYS_IBAT0U       CONFIG_SYS_DBAT0U
 402
 403 /*
 404  * BAT1         1G     Cache-inhibited, guarded
 405  * 0x8000_0000  512M   PCI-Express 1 Memory
 406  * 0xa000_0000  512M   PCI-Express 2 Memory
 407  *      Changed it for operating from 0xd0000000
 408  */
 409 #define CONFIG_SYS_DBAT1L       ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
 410                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 411 #define CONFIG_SYS_DBAT1U       (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
 412 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 413 #define CONFIG_SYS_IBAT1U       CONFIG_SYS_DBAT1U
 414
 415 /*
 416  * BAT2         512M   Cache-inhibited, guarded
 417  * 0xc000_0000  512M   RapidIO Memory
 418  */
 419 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
 420                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 421 #define CONFIG_SYS_DBAT2U       (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
 422 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 423 #define CONFIG_SYS_IBAT2U       CONFIG_SYS_DBAT2U
 424
 425 /*
 426  * BAT3         4M     Cache-inhibited, guarded
 427  * 0xf800_0000  4M     CCSR
 428  */
 429 #define CONFIG_SYS_DBAT3L       ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
 430                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 431 #define CONFIG_SYS_DBAT3U       (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
 432 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
 433 #define CONFIG_SYS_IBAT3U       CONFIG_SYS_DBAT3U
 434
 435 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
 436 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 437                                        | BATL_PP_RW | BATL_CACHEINHIBIT \
 438                                        | BATL_GUARDEDSTORAGE)
 439 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
 440                                        | BATU_BL_1M | BATU_VS | BATU_VP)
 441 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
 442                                        | BATL_PP_RW | BATL_CACHEINHIBIT)
 443 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
 444 #endif
 445
 446 /*
 447  * BAT4         32M    Cache-inhibited, guarded
 448  * 0xe200_0000  16M    PCI-Express 1 I/O
 449  * 0xe300_0000  16M    PCI-Express 2 I/0
 450  *    Note that this is at 0xe0000000
 451  */
 452 #define CONFIG_SYS_DBAT4L       ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
 453                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 454 #define CONFIG_SYS_DBAT4U       (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
 455 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 456 #define CONFIG_SYS_IBAT4U       CONFIG_SYS_DBAT4U
 457
 458 /*
 459  * BAT5         128K   Cacheable, non-guarded
 460  * 0xe401_0000  128K   Init RAM for stack in the CPU DCache (no backing memory)
 461  */
 462 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 463 #define CONFIG_SYS_DBAT5U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 464 #define CONFIG_SYS_IBAT5L       CONFIG_SYS_DBAT5L
 465 #define CONFIG_SYS_IBAT5U       CONFIG_SYS_DBAT5U
 466
 467 /*
 468  * BAT6         32M    Cache-inhibited, guarded
 469  * 0xfe00_0000  32M    FLASH
 470  */
 471 #define CONFIG_SYS_DBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
 472                         | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 473 #define CONFIG_SYS_DBAT6U       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
 474 #define CONFIG_SYS_IBAT6L       ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
 475 #define CONFIG_SYS_IBAT6U       CONFIG_SYS_DBAT6U
 476
 477 /* Map the last 1M of flash where we're running from reset */
 478 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 479                                  | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 480 #define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 481 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
 482                                  | BATL_MEMCOHERENCE)
 483 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
 484
 485 #define CONFIG_SYS_DBAT7L       0x00000000
 486 #define CONFIG_SYS_DBAT7U       0x00000000
 487 #define CONFIG_SYS_IBAT7L       0x00000000
 488 #define CONFIG_SYS_IBAT7U       0x00000000
 489
 490 /*
 491  * Environment
 492  */
 493 #define CONFIG_ENV_IS_IN_FLASH  1
 494 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 495 #define CONFIG_ENV_SECT_SIZE    0x40000 /* 256K(one sector) for env */
 496 #define CONFIG_ENV_SIZE         0x2000
 497
 498 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 499 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 500
 501 #include <config_cmd_default.h>
 502     #define CONFIG_CMD_PING
 503     #define CONFIG_CMD_I2C
 504     #define CONFIG_CMD_REGINFO
 505
 506 #if defined(CONFIG_PCI)
 507     #define CONFIG_CMD_PCI
 508 #endif
 509
 510 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 511
 512 /*
 513  * Miscellaneous configurable options
 514  */
 515 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 516 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 517 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 518
 519 #if defined(CONFIG_CMD_KGDB)
 520     #define CONFIG_SYS_CBSIZE   1024            /* Console I/O Buffer Size */
 521 #else
 522     #define CONFIG_SYS_CBSIZE   256             /* Console I/O Buffer Size */
 523 #endif
 524
 525 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 526 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 527 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 528 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 529
 530 /*
 531  * For booting Linux, the board info and command line data
 532  * have to be in the first 8 MB of memory, since this is
 533  * the maximum mapped by the Linux kernel during initialization.
 534  */
 535 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 536
 537 /* Cache Configuration */
 538 #define CONFIG_SYS_DCACHE_SIZE          32768
 539 #define CONFIG_SYS_CACHELINE_SIZE       32
 540 #if defined(CONFIG_CMD_KGDB)
 541 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 542 #endif
 543
 544 /*
 545  * Internal Definitions
 546  *
 547  * Boot Flags
 548  */
 549 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 550 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 551
 552 #if defined(CONFIG_CMD_KGDB)
 553 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 554 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 555 #endif
 556
 557 /*
 558  * Environment Configuration
 559  */
 560
 561 /* The mac addresses for all ethernet interface */
 562 #if defined(CONFIG_TSEC_ENET)
 563 #define CONFIG_ETHADDR   02:E0:0C:00:00:01
 564 #define CONFIG_ETH1ADDR  02:E0:0C:00:01:FD
 565 #define CONFIG_ETH2ADDR  02:E0:0C:00:02:FD
 566 #define CONFIG_ETH3ADDR  02:E0:0C:00:03:FD
 567 #endif
 568
 569 #define CONFIG_HAS_ETH0         1
 570 #define CONFIG_HAS_ETH1         1
 571 #define CONFIG_HAS_ETH2         1
 572 #define CONFIG_HAS_ETH3         1
 573
 574 #define CONFIG_IPADDR           192.168.0.50
 575
 576 #define CONFIG_HOSTNAME         sbc8641d
 577 #define CONFIG_ROOTPATH         /opt/eldk/ppc_74xx
 578 #define CONFIG_BOOTFILE         uImage
 579
 580 #define CONFIG_SERVERIP         192.168.0.2
 581 #define CONFIG_GATEWAYIP        192.168.0.1
 582 #define CONFIG_NETMASK          255.255.255.0
 583
 584 /* default location for tftp and bootm */
 585 #define CONFIG_LOADADDR         1000000
 586
 587 #define CONFIG_BOOTDELAY 10     /* -1 disables auto-boot */
 588 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 589
 590 #define CONFIG_BAUDRATE 115200
 591
 592 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 593    "netdev=eth0\0"                                                      \
 594    "consoledev=ttyS0\0"                                                 \
 595    "ramdiskaddr=2000000\0"                                              \
 596    "ramdiskfile=uRamdisk\0"                                             \
 597    "dtbaddr=400000\0"                                                   \
 598    "dtbfile=sbc8641d.dtb\0"                                             \
 599    "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0"     \
 600    "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0"    \
 601    "maxcpus=1"
 602
 603 #define CONFIG_NFSBOOTCOMMAND                                           \
 604    "setenv bootargs root=/dev/nfs rw "                                  \
 605       "nfsroot=$serverip:$rootpath "                                    \
 606       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 607       "console=$consoledev,$baudrate $othbootargs;"                     \
 608    "tftp $loadaddr $bootfile;"                                          \
 609    "tftp $dtbaddr $dtbfile;"                                            \
 610    "bootm $loadaddr - $dtbaddr"
 611
 612 #define CONFIG_RAMBOOTCOMMAND                                           \
 613    "setenv bootargs root=/dev/ram rw "                                  \
 614       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 615       "console=$consoledev,$baudrate $othbootargs;"                     \
 616    "tftp $ramdiskaddr $ramdiskfile;"                                    \
 617    "tftp $loadaddr $bootfile;"                                          \
 618    "tftp $dtbaddr $dtbfile;"                                            \
 619    "bootm $loadaddr $ramdiskaddr $dtbaddr"
 620
 621 #define CONFIG_FLASHBOOTCOMMAND                                         \
 622    "setenv bootargs root=/dev/ram rw "                                  \
 623       "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 624       "console=$consoledev,$baudrate $othbootargs;"                     \
 625    "bootm ffd00000 ffb00000 ffa00000"
 626
 627 #define CONFIG_BOOTCOMMAND  CONFIG_FLASHBOOTCOMMAND
 628
 629 #endif  /* __CONFIG_H */