include/configs/scb9328.h

   1 /*
   2  * Copyright (C) 2003 ETC s.r.o.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  * Written by Peter Figuli <peposh@etc.sk>, 2003.
   6  *
   7  * 2003/13/06 Initial MP10 Support copied from wepep250
   8  */
   9
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_IMX              1     /* This is a Motorola MC9328MXL Chip */
  14 #define CONFIG_SCB9328          1     /* on a scb9328tronix board */
  15
  16 #define CONFIG_IMX_SERIAL
  17 #define CONFIG_IMX_SERIAL1
  18 /*
  19  * Select serial console configuration
  20  */
  21
  22 /*
  23  * BOOTP options
  24  */
  25 #define CONFIG_BOOTP_BOOTFILESIZE
  26 #define CONFIG_BOOTP_BOOTPATH
  27 #define CONFIG_BOOTP_GATEWAY
  28 #define CONFIG_BOOTP_HOSTNAME
  29
  30 /*
  31  * Command line configuration.
  32  */
  33 #include <config_cmd_default.h>
  34
  35 #define CONFIG_CMD_NET
  36 #define CONFIG_CMD_PING
  37 #define CONFIG_CMD_DHCP
  38
  39 #undef CONFIG_CMD_CONSOLE
  40 #undef CONFIG_CMD_LOADS
  41 #undef CONFIG_CMD_SOURCE
  42
  43 /*
  44  * Boot options. Setting delay to -1 stops autostart count down.
  45  * NOTE: Sending parameters to kernel depends on kernel version and
  46  * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
  47  * parameters at all! Do not get confused by them so.
  48  */
  49 #define CONFIG_BOOTDELAY   -1
  50 #define CONFIG_BOOTARGS    "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
  51 #define CONFIG_BOOTCOMMAND "bootm 10040000"
  52 #define CONFIG_SHOW_BOOT_PROGRESS
  53 #define CONFIG_NETMASK          255.255.255.0
  54 #define CONFIG_IPADDR           10.10.10.9
  55 #define CONFIG_SERVERIP         10.10.10.10
  56
  57 /*
  58  * General options for u-boot. Modify to save memory foot print
  59  */
  60 #define CONFIG_SYS_LONGHELP                                   /* undef saves memory  */
  61 #define CONFIG_SYS_PROMPT               "scb9328> "           /* prompt string       */
  62 #define CONFIG_SYS_CBSIZE               256                   /* console I/O buffer  */
  63 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size   */
  64 #define CONFIG_SYS_MAXARGS              16                    /* max command args    */
  65 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE             /* boot args buf size  */
  66
  67 #define CONFIG_SYS_MEMTEST_START        0x08100000            /* memtest test area   */
  68 #define CONFIG_SYS_MEMTEST_END          0x08F00000
  69
  70 #define CONFIG_SYS_CPUSPEED             0x141        /* core clock - register value  */
  71
  72 #define CONFIG_BAUDRATE 115200
  73 /*
  74  * Definitions related to passing arguments to kernel.
  75  */
  76 #define CONFIG_CMDLINE_TAG           1   /* send commandline to Kernel       */
  77 #define CONFIG_SETUP_MEMORY_TAGS     1   /* send memory definition to kernel */
  78 #define CONFIG_INITRD_TAG            1   /* send initrd params               */
  79
  80 /*
  81  * Malloc pool need to host env + 128 Kb reserve for other allocations.
  82  */
  83 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128<<10) )
  84
  85 /* SDRAM Setup Values
  86 0x910a8300 Precharge Command CAS 3
  87 0x910a8200 Precharge Command CAS 2
  88
  89 0xa10a8300 AutoRefresh Command CAS 3
  90 0xa10a8200 Set AutoRefresh Command CAS 2 */
  91
  92 #define PRECHARGE_CMD 0x910a8200
  93 #define AUTOREFRESH_CMD 0xa10a8200
  94
  95 /*
  96  * SDRAM Memory Map
  97  */
  98 /* SH FIXME */
  99 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of SDRAM */
 100 #define SCB9328_SDRAM_1         0x08000000      /* SDRAM bank #1           */
 101 #define SCB9328_SDRAM_1_SIZE    0x01000000      /* 16 MB                   */
 102
 103 #define CONFIG_SYS_TEXT_BASE    0x10000000
 104
 105 #define CONFIG_SYS_SDRAM_BASE   SCB9328_SDRAM_1
 106 #define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
 107
 108 /*
 109  * Configuration for FLASH memory for the Synertronixx board
 110  */
 111
 112 /* #define SCB9328_FLASH_32M */
 113
 114 /* 32MB */
 115 #ifdef SCB9328_FLASH_32M
 116 #define CONFIG_SYS_MAX_FLASH_BANKS              1       /* FLASH banks count (not chip count)*/
 117 #define CONFIG_SYS_MAX_FLASH_SECT               256     /* number of sector in FLASH bank    */
 118 #define SCB9328_FLASH_BUS_WIDTH         2       /* we use 16 bit FLASH memory...     */
 119 #define SCB9328_FLASH_INTERLEAVE        1       /* ... made of 1 chip                */
 120 #define SCB9328_FLASH_BANK_SIZE  0x02000000     /* size of one flash bank            */
 121 #define SCB9328_FLASH_SECT_SIZE  0x00020000     /* size of erase sector              */
 122 #define SCB9328_FLASH_BASE       0x10000000     /* location of flash memory          */
 123 #define SCB9328_FLASH_UNLOCK            1       /* perform hw unlock first           */
 124 #else
 125
 126 /* 16MB */
 127 #define CONFIG_SYS_MAX_FLASH_BANKS              1       /* FLASH banks count (not chip count)*/
 128 #define CONFIG_SYS_MAX_FLASH_SECT               128     /* number of sector in FLASH bank    */
 129 #define SCB9328_FLASH_BUS_WIDTH         2       /* we use 16 bit FLASH memory...     */
 130 #define SCB9328_FLASH_INTERLEAVE        1       /* ... made of 1 chip                */
 131 #define SCB9328_FLASH_BANK_SIZE  0x01000000     /* size of one flash bank            */
 132 #define SCB9328_FLASH_SECT_SIZE  0x00020000     /* size of erase sector              */
 133 #define SCB9328_FLASH_BASE       0x10000000     /* location of flash memory          */
 134 #define SCB9328_FLASH_UNLOCK            1       /* perform hw unlock first           */
 135 #endif /* SCB9328_FLASH_32M */
 136
 137 /* This should be defined if CFI FLASH device is present. Actually benefit
 138    is not so clear to me. In other words we can provide more informations
 139    to user, but this expects more complex flash handling we do not provide
 140    now.*/
 141 #undef  CONFIG_SYS_FLASH_CFI
 142
 143 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000    /* timeout for Erase operation */
 144 #define CONFIG_SYS_FLASH_WRITE_TOUT     240000    /* timeout for Write operation */
 145
 146 #define CONFIG_SYS_FLASH_BASE           SCB9328_FLASH_BASE
 147
 148 /*
 149  * This is setting for JFFS2 support in u-boot.
 150  * Right now there is no gain for user, but later on booting kernel might be
 151  * possible. Consider using XIP kernel running from flash to save RAM
 152  * footprint.
 153  * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 154  */
 155 #define CONFIG_SYS_JFFS2_FIRST_BANK             0
 156 #define CONFIG_SYS_JFFS2_FIRST_SECTOR           5
 157 #define CONFIG_SYS_JFFS2_NUM_BANKS              1
 158
 159 /*
 160  * Environment setup. Definitions of monitor location and size with
 161  * definition of environment setup ends up in 2 possibilities.
 162  * 1. Embeded environment - in u-boot code is space for environment
 163  * 2. Environment is read from predefined sector of flash
 164  * Right now we support 2. possiblity, but expecting no env placed
 165  * on mentioned address right now. This also needs to provide whole
 166  * sector for it - for us 256Kb is really waste of memory. U-boot uses
 167  * default env. and until kernel parameters could be sent to kernel
 168  * env. has no sense to us.
 169  */
 170
 171 /* Setup for PA23 which is Reset Default PA23 but has to become
 172    CS5 */
 173
 174 #define CONFIG_SYS_GPR_A_VAL            0x00800000
 175 #define CONFIG_SYS_GIUS_A_VAL           0x0043fffe
 176
 177 #define CONFIG_SYS_MONITOR_BASE 0x10000000
 178 #define CONFIG_SYS_MONITOR_LEN          0x20000         /* 128b ( 1 flash sector )  */
 179 #define CONFIG_ENV_IS_IN_FLASH  1
 180 #define CONFIG_ENV_ADDR         0x10020000      /* absolute address for now  */
 181 #define CONFIG_ENV_SIZE         0x20000
 182
 183 #define  CONFIG_ENV_OVERWRITE  1                /* env is not writable now   */
 184
 185 /*
 186  * CSxU_VAL:
 187  * 63| x        x x x | x x x x | x x  x    x | x x x x | x x x x | x x x x | x x x x | x x x x|32
 188  *   |DTACK_SEL|0|BCD |   BCS   | PSZ|PME|SYNC|  DOL    | CNC|    WSC       | 0| WWS  |   EDC  |
 189  *
 190  * CSxL_VAL:
 191  * 31| x x x x | x x x x | x x x x | x x x x | x x x x |  x x x x | x x  x x | x x  x    x| 0
 192  *   |   OEA   |   OEN   |   WEA   |   WEN   |   CSA   |EBC| DSZ  | 0|SP|0|WP| 0 0|PA|CSEN|
 193  */
 194
 195 #define CONFIG_SYS_CS0U_VAL 0x000F2000
 196 #define CONFIG_SYS_CS0L_VAL 0x11110d01
 197 #define CONFIG_SYS_CS1U_VAL 0x000F0a00
 198 #define CONFIG_SYS_CS1L_VAL 0x11110601
 199 #define CONFIG_SYS_CS2U_VAL 0x0
 200 #define CONFIG_SYS_CS2L_VAL 0x0
 201
 202 #define CONFIG_SYS_CS3U_VAL 0x000FFFFF
 203 #define CONFIG_SYS_CS3L_VAL 0x00000303
 204
 205 #define CONFIG_SYS_CS4U_VAL 0x000F0a00
 206 #define CONFIG_SYS_CS4L_VAL 0x11110301
 207
 208 /* CNC == 3 too long
 209    #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
 210
 211 /* #define CONFIG_SYS_CS5U_VAL 0x00008400
 212    mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
 213    kaum langsamer ist */
 214 /* #define CONFIG_SYS_CS5U_VAL 0x00009400
 215    #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
 216
 217 #define CONFIG_SYS_CS5U_VAL 0x00008400
 218 #define CONFIG_SYS_CS5L_VAL 0x00000D03
 219
 220 #define CONFIG_DRIVER_DM9000            1
 221 #define CONFIG_DM9000_BASE              0x16000000
 222 #define DM9000_IO                       CONFIG_DM9000_BASE
 223 #define DM9000_DATA                     (CONFIG_DM9000_BASE+4)
 224
 225 /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
 226    f_ref=16,777MHz
 227
 228    0x002a141f: 191,9944MHz
 229    0x040b2007: 144MHz
 230    0x042a141f: 96MHz
 231    0x0811140d: 64MHz
 232    0x040e200e: 150MHz
 233    0x00321431: 200MHz
 234
 235    0x08001800: 64MHz mit 16er Quarz
 236    0x04001800: 96MHz mit 16er Quarz
 237    0x04002400: 144MHz mit 16er Quarz
 238
 239    31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
 240       |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|     */
 241
 242 #define CPU200
 243
 244 #ifdef CPU200
 245 #define CONFIG_SYS_MPCTL0_VAL 0x00321431
 246 #else
 247 #define CONFIG_SYS_MPCTL0_VAL 0x040e200e
 248 #endif
 249
 250 /* #define BUS64 */
 251 #define BUS72
 252
 253 #ifdef BUS72
 254 #define CONFIG_SYS_SPCTL0_VAL 0x04002400
 255 #endif
 256
 257 #ifdef BUS96
 258 #define CONFIG_SYS_SPCTL0_VAL 0x04001800
 259 #endif
 260
 261 #ifdef BUS64
 262 #define CONFIG_SYS_SPCTL0_VAL 0x08001800
 263 #endif
 264
 265 /* Das ist der BCLK Divider, der aus der System PLL
 266    BCLK und HCLK erzeugt:
 267    31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
 268    0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
 269    0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
 270    0x2f001003 : 192MHz/5=38,4MHz
 271    0x2f000003 : 64MHz/1
 272    Bit 22: SPLL Restart
 273    Bit 21: MPLL Restart */
 274
 275 #ifdef BUS64
 276 #define CONFIG_SYS_CSCR_VAL 0x2f030003
 277 #endif
 278
 279 #ifdef BUS72
 280 #define CONFIG_SYS_CSCR_VAL 0x2f030403
 281 #endif
 282
 283 /*
 284  * Well this has to be defined, but on the other hand it is used differently
 285  * one may expect. For instance loadb command do not cares :-)
 286  * So advice is - do not relay on this...
 287  */
 288 #define CONFIG_SYS_LOAD_ADDR 0x08400000
 289
 290 #define MHZ16QUARZINUSE
 291
 292 #ifdef MHZ16QUARZINUSE
 293 #define CONFIG_SYSPLL_CLK_FREQ 16000000
 294 #else
 295 #define CONFIG_SYSPLL_CLK_FREQ 16780000
 296 #endif
 297
 298 #define CONFIG_SYS_CLK_FREQ 16780000
 299
 300 /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
 301 #define CONFIG_SYS_FMCR_VAL 0x00000001
 302
 303 /* Bit[0:3] contain PERCLK1DIV for UART 1
 304    0x000b00b ->b<- -> 192MHz/12=16MHz
 305    0x000b00b ->8<- -> 144MHz/09=16MHz
 306    0x000b00b ->3<- -> 64MHz/4=16MHz */
 307
 308 #ifdef BUS96
 309 #define CONFIG_SYS_PCDR_VAL 0x000b00b5
 310 #endif
 311
 312 #ifdef BUS64
 313 #define CONFIG_SYS_PCDR_VAL 0x000b00b3
 314 #endif
 315
 316 #ifdef BUS72
 317 #define CONFIG_SYS_PCDR_VAL 0x000b00b8
 318 #endif
 319
 320 #endif  /* __CONFIG_H */