include/configs/sequoia.h

   1 /*
   2  * (C) Copyright 2006-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /************************************************************************
  26  * sequoia.h - configuration for Sequoia & Rainier boards
  27  ***********************************************************************/
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*-----------------------------------------------------------------------
  32  * High Level Configuration Options
  33  *----------------------------------------------------------------------*/
  34 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  35 #ifndef CONFIG_RAINIER
  36 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  37 #else
  38 #define CONFIG_440GRX           1               /* Specific PPC440GRx   */
  39 #endif
  40 #define CONFIG_440              1               /* ... PPC440 family    */
  41 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  42 /* Detect Sequoia PLL input clock automatically via CPLD bit            */
  43 #define CONFIG_SYS_CLK_FREQ    ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
  44                                 33333333 : 33000000)
  45
  46 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  47 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  48
  49 /*-----------------------------------------------------------------------
  50  * Base addresses -- Note these are effective addresses where the
  51  * actual resources get mapped (not physical addresses)
  52  *----------------------------------------------------------------------*/
  53 #define CFG_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Monitor   */
  54 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
  55
  56 #define CFG_BOOT_BASE_ADDR      0xf0000000
  57 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  58 #define CFG_FLASH_BASE          0xfc000000      /* start of FLASH       */
  59 #define CFG_MONITOR_BASE        TEXT_BASE
  60 #define CFG_NAND_ADDR           0xd0000000      /* NAND Flash           */
  61 #define CFG_OCM_BASE            0xe0010000      /* ocm                  */
  62 #define CFG_OCM_DATA_ADDR       CFG_OCM_BASE
  63 #define CFG_PCI_BASE            0xe0000000      /* Internal PCI regs    */
  64 #define CFG_PCI_MEMBASE         0x80000000      /* mapped pci memory    */
  65 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  66 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  67 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  68
  69 /* Don't change either of these */
  70 #define CFG_PERIPHERAL_BASE     0xef600000      /* internal peripherals */
  71
  72 #define CFG_USB2D0_BASE         0xe0000100
  73 #define CFG_USB_DEVICE          0xe0000000
  74 #define CFG_USB_HOST            0xe0000400
  75 #define CFG_BCSR_BASE           0xc0000000
  76
  77 /*-----------------------------------------------------------------------
  78  * Initial RAM & stack pointer
  79  *----------------------------------------------------------------------*/
  80 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  81 #define CFG_INIT_RAM_ADDR       CFG_OCM_BASE    /* OCM                  */
  82 #define CFG_INIT_RAM_END        (4 << 10)
  83 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data */
  84 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  85 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  86
  87 /*-----------------------------------------------------------------------
  88  * Serial Port
  89  *----------------------------------------------------------------------*/
  90 #define CFG_EXT_SERIAL_CLOCK    11059200        /* ext. 11.059MHz clk   */
  91 #define CONFIG_BAUDRATE         115200
  92 #define CONFIG_SERIAL_MULTI     1
  93 /* define this if you want console on UART1 */
  94 #undef CONFIG_UART1_CONSOLE
  95
  96 #define CFG_BAUDRATE_TABLE                                              \
  97         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  98
  99 /*-----------------------------------------------------------------------
 100  * Environment
 101  *----------------------------------------------------------------------*/
 102 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 103 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 104 #else
 105 #define CFG_ENV_IS_IN_NAND      1       /* use NAND for environment vars        */
 106 #define CFG_ENV_IS_EMBEDDED     1       /* use embedded environment */
 107 #endif
 108
 109 /*-----------------------------------------------------------------------
 110  * FLASH related
 111  *----------------------------------------------------------------------*/
 112 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 113 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 114
 115 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 116
 117 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 118 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 119
 120 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 121 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 122
 123 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 124 #define CFG_FLASH_PROTECTION    1       /* use hardware flash protection        */
 125
 126 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 127 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
 128
 129 #ifdef CFG_ENV_IS_IN_FLASH
 130 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector          */
 131 #define CFG_ENV_ADDR            ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 132 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 133
 134 /* Address and size of Redundant Environment Sector     */
 135 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 136 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 137 #endif
 138
 139 /*
 140  * IPL (Initial Program Loader, integrated inside CPU)
 141  * Will load first 4k from NAND (SPL) into cache and execute it from there.
 142  *
 143  * SPL (Secondary Program Loader)
 144  * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 145  * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 146  * controller and the NAND controller so that the special U-Boot image can be
 147  * loaded from NAND to SDRAM.
 148  *
 149  * NUB (NAND U-Boot)
 150  * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 151  * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 152  *
 153  * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 154  * set up. While still running from cache, I experienced problems accessing
 155  * the NAND controller. sr - 2006-08-25
 156  */
 157 #define CFG_NAND_BOOT_SPL_SRC   0xfffff000      /* SPL location                 */
 158 #define CFG_NAND_BOOT_SPL_SIZE  (4 << 10)       /* SPL size                     */
 159 #define CFG_NAND_BOOT_SPL_DST   (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here    */
 160 #define CFG_NAND_U_BOOT_DST     0x01000000      /* Load NUB to this addr        */
 161 #define CFG_NAND_U_BOOT_START   CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
 162 #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
 163
 164 /*
 165  * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 166  */
 167 #define CFG_NAND_U_BOOT_OFFS    (16 << 10)      /* Offset to RAM U-Boot image   */
 168 #define CFG_NAND_U_BOOT_SIZE    (384 << 10)     /* Size of RAM U-Boot image     */
 169
 170 /*
 171  * Now the NAND chip has to be defined (no autodetection used!)
 172  */
 173 #define CFG_NAND_PAGE_SIZE      512             /* NAND chip page size          */
 174 #define CFG_NAND_BLOCK_SIZE     (16 << 10)      /* NAND chip block size         */
 175 #define CFG_NAND_PAGE_COUNT     32              /* NAND chip page count         */
 176 #define CFG_NAND_BAD_BLOCK_POS  5               /* Location of bad block marker */
 177 #undef CFG_NAND_4_ADDR_CYCLE                    /* No fourth addr used (<=32MB) */
 178
 179 #define CFG_NAND_ECCSIZE        256
 180 #define CFG_NAND_ECCBYTES       3
 181 #define CFG_NAND_ECCSTEPS       (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
 182 #define CFG_NAND_OOBSIZE        16
 183 #define CFG_NAND_ECCTOTAL       (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
 184 #define CFG_NAND_ECCPOS         {0, 1, 2, 3, 6, 7}
 185
 186 #ifdef CFG_ENV_IS_IN_NAND
 187 /*
 188  * For NAND booting the environment is embedded in the U-Boot image. Please take
 189  * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 190  */
 191 #define CFG_ENV_SIZE            CFG_NAND_BLOCK_SIZE
 192 #define CFG_ENV_OFFSET          (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
 193 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET + CFG_ENV_SIZE)
 194 #endif
 195
 196 /*-----------------------------------------------------------------------
 197  * DDR SDRAM
 198  *----------------------------------------------------------------------*/
 199 #define CFG_MBYTES_SDRAM        (256)           /* 256MB                        */
 200 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 201 #define CONFIG_DDR_DATA_EYE                     /* use DDR2 optimization        */
 202 #endif
 203
 204 /*-----------------------------------------------------------------------
 205  * I2C
 206  *----------------------------------------------------------------------*/
 207 #define CONFIG_HARD_I2C         1               /* I2C with hardware support    */
 208 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 209 #define CFG_I2C_SPEED           400000          /* I2C speed and slave address  */
 210 #define CFG_I2C_SLAVE           0x7F
 211
 212 #define CFG_I2C_MULTI_EEPROMS
 213 #define CFG_I2C_EEPROM_ADDR     (0xa8>>1)
 214 #define CFG_I2C_EEPROM_ADDR_LEN 1
 215 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 216 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 217 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 218
 219 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 220 #define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 221 #define CONFIG_DTT_AD7414       1               /* use AD7414           */
 222 #define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 223 #define CFG_DTT_MAX_TEMP        70
 224 #define CFG_DTT_LOW_TEMP        -30
 225 #define CFG_DTT_HYSTERESIS      3
 226
 227 #define CONFIG_PREBOOT  "echo;"                                         \
 228         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 229         "echo"
 230
 231 #undef  CONFIG_BOOTARGS
 232
 233 /* Setup some board specific values for the default environment variables */
 234 #ifndef CONFIG_RAINIER
 235 #define CONFIG_HOSTNAME         sequoia
 236 #define CFG_BOOTFILE            "bootfile=/tftpboot/sequoia/uImage\0"
 237 #define CFG_ROOTPATH            "rootpath=/opt/eldk/ppc_4xxFP\0"
 238 #else
 239 #define CONFIG_HOSTNAME         rainier
 240 #define CFG_BOOTFILE            "bootfile=/tftpboot/rainier/uImage\0"
 241 #define CFG_ROOTPATH            "rootpath=/opt/eldk/ppc_4xx\0"
 242 #endif
 243
 244 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 245         CFG_BOOTFILE                                                    \
 246         CFG_ROOTPATH                                                    \
 247         "netdev=eth0\0"                                                 \
 248         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 249                 "nfsroot=${serverip}:${rootpath}\0"                     \
 250         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 251         "addip=setenv bootargs ${bootargs} "                            \
 252                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 253                 ":${hostname}:${netdev}:off panic=1\0"                  \
 254         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 255         "flash_nfs=run nfsargs addip addtty;"                           \
 256                 "bootm ${kernel_addr}\0"                                \
 257         "flash_self=run ramargs addip addtty;"                          \
 258                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 259         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 260                 "bootm\0"                                               \
 261         "kernel_addr=FC000000\0"                                        \
 262         "ramdisk_addr=FC180000\0"                                       \
 263         "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 264         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 265                 "cp.b 200000 FFFA0000 60000\0"                          \
 266         "upd=run load;run update\0"                                     \
 267         ""
 268 #define CONFIG_BOOTCOMMAND      "run flash_self"
 269
 270 #if 0
 271 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 272 #else
 273 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 274 #endif
 275
 276 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 277 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 278
 279 #define CONFIG_M88E1111_PHY     1
 280 #define CONFIG_IBM_EMAC4_V4     1
 281 #define CONFIG_MII              1       /* MII PHY management           */
 282 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 283
 284 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 285 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 286
 287 #define CONFIG_HAS_ETH0
 288 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 289
 290 #define CONFIG_NET_MULTI        1
 291 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 292 #define CONFIG_PHY1_ADDR        1
 293
 294 /* USB */
 295 #ifdef CONFIG_440EPX
 296 #define CONFIG_USB_OHCI
 297 #define CONFIG_USB_STORAGE
 298
 299 /* Comment this out to enable USB 1.1 device */
 300 #define USB_2_0_DEVICE
 301
 302 #define CMD_USB                 CFG_CMD_USB
 303 #else
 304 #define CMD_USB                 0       /* no USB on 440GRx             */
 305 #endif /* CONFIG_440EPX */
 306
 307 /* Partitions */
 308 #define CONFIG_MAC_PARTITION
 309 #define CONFIG_DOS_PARTITION
 310 #define CONFIG_ISO_PARTITION
 311
 312 #define CONFIG_COMMANDS       (CONFIG_CMD_DFL   |       \
 313                                CFG_CMD_ASKENV   |       \
 314                                CFG_CMD_DHCP     |       \
 315                                CFG_CMD_DTT      |       \
 316                                CFG_CMD_DIAG     |       \
 317                                CFG_CMD_EEPROM   |       \
 318                                CFG_CMD_ELF      |       \
 319                                CFG_CMD_FAT      |       \
 320                                CFG_CMD_I2C      |       \
 321                                CFG_CMD_IRQ      |       \
 322                                CFG_CMD_MII      |       \
 323                                CFG_CMD_NAND     |       \
 324                                CFG_CMD_NET      |       \
 325                                CFG_CMD_NFS      |       \
 326                                CFG_CMD_PCI      |       \
 327                                CFG_CMD_PING     |       \
 328                                CFG_CMD_REGINFO  |       \
 329                                CFG_CMD_SDRAM    |       \
 330                                CMD_USB)
 331
 332 /* POST support */
 333 #define CONFIG_POST             (CFG_POST_MEMORY   | \
 334                                  CFG_POST_CPU      | \
 335                                  CFG_POST_UART     | \
 336                                  CFG_POST_I2C      | \
 337                                  CFG_POST_CACHE    | \
 338                                  CFG_POST_FPU      | \
 339                                  CFG_POST_ETHER    | \
 340                                  CFG_POST_SPR)
 341
 342 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
 343 #define CONFIG_LOGBUFFER
 344 #define CFG_POST_CACHE_ADDR     0x10000000 /* free virtual address      */
 345
 346 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 347
 348 #define CONFIG_SUPPORT_VFAT
 349
 350 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 351 #include <cmd_confdefs.h>
 352
 353 /*-----------------------------------------------------------------------
 354  * Miscellaneous configurable options
 355  *----------------------------------------------------------------------*/
 356 #define CFG_LONGHELP                    /* undef to save memory         */
 357 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 358 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 359 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 360 #else
 361 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 362 #endif
 363 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 364 #define CFG_MAXARGS             16      /* max number of command args   */
 365 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 366
 367 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 368 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 369
 370 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 371 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 372
 373 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 374
 375 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 376 #define CONFIG_LOOPW            1       /* enable loopw command         */
 377 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 378 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 379 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 380
 381 /*-----------------------------------------------------------------------
 382  * PCI stuff
 383  *----------------------------------------------------------------------*/
 384 /* General PCI */
 385 #define CONFIG_PCI                      /* include pci support          */
 386 #undef CONFIG_PCI_PNP                   /* do (not) pci plug-and-play   */
 387 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 388 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 389
 390 /* Board-specific PCI */
 391 #define CFG_PCI_TARGET_INIT
 392 #define CFG_PCI_MASTER_INIT
 393
 394 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC                         */
 395 #define CFG_PCI_SUBSYS_ID       0xcafe  /* Whatever                     */
 396
 397 /*
 398  * For booting Linux, the board info and command line data
 399  * have to be in the first 8 MB of memory, since this is
 400  * the maximum mapped by the Linux kernel during initialization.
 401  */
 402 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 403
 404 /*-----------------------------------------------------------------------
 405  * External Bus Controller (EBC) Setup
 406  *----------------------------------------------------------------------*/
 407
 408 /*
 409  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 410  */
 411 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 412 #define CFG_NAND_CS             3               /* NAND chip connected to CSx   */
 413 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 414 #define CFG_EBC_PB0AP           0x03017200
 415 #define CFG_EBC_PB0CR           (CFG_FLASH_BASE | 0xda000)
 416
 417 /* Memory Bank 3 (NAND-FLASH) initialization                                    */
 418 #define CFG_EBC_PB3AP           0x018003c0
 419 #define CFG_EBC_PB3CR           (CFG_NAND_ADDR | 0x1c000)
 420 #else
 421 #define CFG_NAND_CS             0               /* NAND chip connected to CSx   */
 422 /* Memory Bank 3 (NOR-FLASH) initialization                                     */
 423 #define CFG_EBC_PB3AP           0x03017200
 424 #define CFG_EBC_PB3CR           (CFG_FLASH_BASE | 0xda000)
 425
 426 /* Memory Bank 0 (NAND-FLASH) initialization                                    */
 427 #define CFG_EBC_PB0AP           0x018003c0
 428 #define CFG_EBC_PB0CR           (CFG_NAND_ADDR | 0x1c000)
 429 #endif
 430
 431 /* Memory Bank 2 (CPLD) initialization                                          */
 432 #define CFG_EBC_PB2AP           0x24814580
 433 #define CFG_EBC_PB2CR           (CFG_BCSR_BASE | 0x38000)
 434
 435 /*-----------------------------------------------------------------------
 436  * NAND FLASH
 437  *----------------------------------------------------------------------*/
 438 #define CFG_MAX_NAND_DEVICE     1
 439 #define NAND_MAX_CHIPS          1
 440 #define CFG_NAND_BASE           (CFG_NAND_ADDR + CFG_NAND_CS)
 441 #define CFG_NAND_SELECT_DEVICE  1       /* nand driver supports mutipl. chips   */
 442
 443 /*-----------------------------------------------------------------------
 444  * Cache Configuration
 445  *----------------------------------------------------------------------*/
 446 #define CFG_DCACHE_SIZE         (32<<10)  /* For AMCC 440 CPUs                  */
 447 #define CFG_CACHELINE_SIZE      32            /* ...                                */
 448 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 449 #define CFG_CACHELINE_SHIFT     5             /* log base 2 of the above value  */
 450 #endif
 451
 452 /*
 453  * Internal Definitions
 454  *
 455  * Boot Flags
 456  */
 457 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 458 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 459
 460 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 461 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 462 #define CONFIG_KGDB_SER_INDEX   2           /* which serial port to use */
 463 #endif
 464 #endif  /* __CONFIG_H */