include/configs/sequoia.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 /*
  13  * sequoia.h - configuration for Sequoia & Rainier boards
  14  */
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * High Level Configuration Options
  20  */
  21 /* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  22 #ifndef CONFIG_RAINIER
  23 #define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  24 #define CONFIG_HOSTNAME         sequoia
  25 #else
  26 #define CONFIG_440GRX           1       /* Specific PPC440GRx           */
  27 #define CONFIG_HOSTNAME         rainier
  28 #endif
  29 #define CONFIG_440              1       /* ... PPC440 family            */
  30
  31 #ifndef CONFIG_SYS_TEXT_BASE
  32 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  33 #endif
  34
  35 /*
  36  * Include common defines/options for all AMCC eval boards
  37  */
  38 #include "amcc-common.h"
  39
  40 /* Detect Sequoia PLL input clock automatically via CPLD bit            */
  41 #define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
  42                                 33333333 : 33000000)
  43
  44 /*
  45  * Define this if you want support for video console with radeon 9200 pci card
  46  * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
  47  */
  48
  49 #ifdef CONFIG_VIDEO
  50 /*
  51  * 44x dcache supported is working now on sequoia, but we don't enable
  52  * it yet since it needs further testing
  53  */
  54 #define CONFIG_4xx_DCACHE               /* enable dcache                */
  55 #endif
  56
  57 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  58
  59 /*
  60  * Base addresses -- Note these are effective addresses where the actual
  61  * resources get mapped (not physical addresses).
  62  */
  63 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0x0003
  64 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  65 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  66 #define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  67 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  68 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  69 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  70 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  71 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  72 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  73 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  74
  75 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  76 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  77 #define CONFIG_SYS_USB_HOST             0xe0000400
  78 #define CONFIG_SYS_BCSR_BASE            0xc0000000
  79
  80 /*
  81  * Initial RAM & stack pointer
  82  */
  83 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  84 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  85 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  86 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  87 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  88
  89 /*
  90  * Serial Port
  91  */
  92 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  93 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
  94
  95 /*
  96  * Environment
  97  */
  98 #if defined(CONFIG_SYS_RAMBOOT)
  99 #define CONFIG_ENV_IS_NOWHERE           /* Store env in memory only     */
 100 #define CONFIG_ENV_SIZE         (8 << 10)
 101 #else
 102 #define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environ vars   */
 103 #endif
 104
 105 #if defined(CONFIG_CMD_FLASH)
 106 /*
 107  * FLASH related
 108  */
 109 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 110 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 111
 112 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 113
 114 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 115 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 116
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 119
 120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 121 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 122
 123 #define CONFIG_SYS_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 124 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 125 #endif /* CONFIG_CMD_FLASH */
 126
 127 #ifdef CONFIG_ENV_IS_IN_FLASH
 128 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 129 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 130 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 131
 132 /* Address and size of Redundant Environment Sector     */
 133 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 134 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 135 #endif
 136
 137 /*
 138  * DDR SDRAM
 139  */
 140 #define CONFIG_SYS_MBYTES_SDRAM        (256)    /* 256MB                        */
 141 #if !defined(CONFIG_SYS_RAMBOOT)
 142 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 143 #endif
 144 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes     */
 145                                         /* 440EPx errata CHIP 11        */
 146
 147 /*
 148  * I2C
 149  */
 150 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 151
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 155 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 156
 157 /* I2C bootstrap EEPROM */
 158 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 159 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 160 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 161
 162 /*
 163  * Default environment variables
 164  */
 165 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 166         CONFIG_AMCC_DEF_ENV                                             \
 167         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 168         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 169         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 170         "kernel_addr=FC000000\0"                                        \
 171         "ramdisk_addr=FC180000\0"                                       \
 172         ""
 173
 174 #define CONFIG_M88E1111_PHY     1
 175 #define CONFIG_IBM_EMAC4_V4     1
 176 #define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 177
 178 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 179 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 180
 181 #define CONFIG_HAS_ETH0
 182 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 183 #define CONFIG_PHY1_ADDR        1
 184
 185 /* USB */
 186 #ifdef CONFIG_440EPX
 187 #ifdef CONFIG_USB_EHCI_HCD
 188 #define CONFIG_USB_EHCI_PPC4XX
 189 #define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 190 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 191 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
 192 #define CONFIG_EHCI_DESC_BIG_ENDIAN
 193 #else /* CONFIG_USB_EHCI_HCD */
 194 #define CONFIG_USB_OHCI_NEW
 195 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 196
 197 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 198 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 199 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 200 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 201 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 202 #endif
 203
 204 /* Comment this out to enable USB 1.1 device */
 205 #define USB_2_0_DEVICE
 206
 207 #endif /* CONFIG_440EPX */
 208
 209 /* Partitions */
 210
 211 /*
 212  * Commands additional to the ones defined in amcc-common.h
 213  */
 214 #define CONFIG_CMD_NAND
 215 #define CONFIG_CMD_PCI
 216 #define CONFIG_CMD_SDRAM
 217
 218 #ifdef CONFIG_440EPX
 219 #endif
 220
 221 #ifndef CONFIG_RAINIER
 222 #define CONFIG_SYS_POST_FPU_ON          CONFIG_SYS_POST_FPU
 223 #else
 224 #define CONFIG_SYS_POST_FPU_ON          0
 225 #endif
 226
 227 /*
 228  * Don't run the memory POST on the NAND-booting version. It will
 229  * overwrite part of the U-Boot image which is already loaded from NAND
 230  * to SDRAM.
 231  */
 232 #if defined(CONFIG_SYS_RAMBOOT)
 233 #define CONFIG_SYS_POST_MEMORY_ON       0
 234 #else
 235 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 236 #endif
 237
 238 /* POST support */
 239 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE     | \
 240                                  CONFIG_SYS_POST_CPU       | \
 241                                  CONFIG_SYS_POST_ETHER     | \
 242                                  CONFIG_SYS_POST_FPU_ON    | \
 243                                  CONFIG_SYS_POST_I2C       | \
 244                                  CONFIG_SYS_POST_MEMORY_ON | \
 245                                  CONFIG_SYS_POST_SPR       | \
 246                                  CONFIG_SYS_POST_UART)
 247
 248 #define CONFIG_LOGBUFFER
 249 #define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 250
 251 #define CONFIG_SUPPORT_VFAT
 252
 253 /*
 254  * PCI stuff
 255  */
 256 /* General PCI */
 257 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 258 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 259 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 260 #define CONFIG_SYS_PCI_TARGBASE 0x80000000      /* PCIaddr mapped to    */
 261                                                 /*   CONFIG_SYS_PCI_MEMBASE     */
 262 /* Board-specific PCI */
 263 #define CONFIG_SYS_PCI_TARGET_INIT
 264 #define CONFIG_SYS_PCI_MASTER_INIT
 265 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 266
 267 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC                         */
 268 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever                     */
 269
 270 /*
 271  * External Bus Controller (EBC) Setup
 272  */
 273
 274 /*
 275  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 276  */
 277 #if !defined(CONFIG_SYS_RAMBOOT)
 278 #define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx   */
 279 /* Memory Bank 0 (NOR-FLASH) initialization                             */
 280 #define CONFIG_SYS_EBC_PB0AP            0x03017200
 281 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 282
 283 /* Memory Bank 3 (NAND-FLASH) initialization                            */
 284 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 285 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 286 #else
 287 #define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx   */
 288 /* Memory Bank 3 (NOR-FLASH) initialization                             */
 289 #define CONFIG_SYS_EBC_PB3AP            0x03017200
 290 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 291
 292 /* Memory Bank 0 (NAND-FLASH) initialization                            */
 293 #define CONFIG_SYS_EBC_PB0AP            0x018003c0
 294 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 295 #endif
 296
 297 /* Memory Bank 2 (CPLD) initialization                                  */
 298 #define CONFIG_SYS_EBC_PB2AP            0x24814580
 299 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x38000)
 300
 301 #define CONFIG_SYS_BCSR5_PCI66EN        0x80
 302
 303 /*
 304  * NAND FLASH
 305  */
 306 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 307 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 308 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 309
 310 /*
 311  * PPC440 GPIO Configuration
 312  */
 313 /* test-only: take GPIO init from pcs440ep ???? in config file */
 314 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 315 {                                                                                       \
 316 /* GPIO Core 0 */                                                                       \
 317 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 318 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 319 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 320 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 321 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 322 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 323 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 324 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 325 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 326 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 327 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 328 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 329 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 330 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 331 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14                                */      \
 332 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 333 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 334 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 335 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 336 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 337 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 338 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 339 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 340 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 341 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 342 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 343 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 344 {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 345 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28                USB2D_TXVALID   */      \
 346 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 347 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 348 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 349 },                                                                                      \
 350 {                                                                                       \
 351 /* GPIO Core 1 */                                                                       \
 352 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 353 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 354 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
 355 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 356 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N    EBC_DATA(0)     UART3_SIN*/ \
 357 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 358 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT    */      \
 359 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN      */      \
 360 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 361 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 362 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 363 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 364 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 365 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 366 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 367 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 368 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 369 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 370 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 371 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 372 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 373 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 374 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 375 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 376 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 377 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 378 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 379 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 380 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 381 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 382 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 383 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 384 }                                                                                       \
 385 }
 386
 387 #ifdef CONFIG_VIDEO
 388 #define CONFIG_BIOSEMU                  /* x86 bios emulator for vga bios */
 389 #define CONFIG_ATI_RADEON_FB            /* use radeon framebuffer driver */
 390 #define VIDEO_IO_OFFSET                 0xe8000000
 391 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS          VIDEO_IO_OFFSET
 392 #define CONFIG_VIDEO_LOGO
 393 #define CONFIG_SPLASH_SCREEN
 394 #endif
 395
 396 #endif /* __CONFIG_H */