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Convert CONFIG_SYS_CONSOLE_INFO_QUIET to Kconfig
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1 /*
2 * Configuation settings for the Renesas Technology R0P7785LC0011RL board
3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __SH7785LCR_H
10 #define __SH7785LCR_H
11
12 #undef DEBUG
13 #define CONFIG_CPU_SH7785 1
14 #define CONFIG_SH7785LCR 1
15
16 #define CONFIG_CMD_PCI
17 #define CONFIG_CMD_SDRAM
18 #define CONFIG_CMD_SH_ZIMAGEBOOT
19
20 #define CONFIG_DOS_PARTITION
21 #define CONFIG_MAC_PARTITION
22
23 #define CONFIG_BAUDRATE 115200
24 #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
25
26 #define CONFIG_EXTRA_ENV_SETTINGS \
27 "bootdevice=0:1\0" \
28 "usbload=usb reset;usbboot;usb stop;bootm\0"
29
30 #undef CONFIG_SHOW_BOOT_PROGRESS
31
32 /* MEMORY */
33 #if defined(CONFIG_SH_32BIT)
34 #define CONFIG_SYS_TEXT_BASE 0x8FF80000
35 /* 0x40000000 - 0x47FFFFFF does not use */
36 #define CONFIG_SH_SDRAM_OFFSET (0x8000000)
37 #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
38 #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
39 #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
40 #define SH7785LCR_FLASH_BASE_1 (0xa0000000)
41 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
42 #define SH7785LCR_USB_BASE (0xa6000000)
43 #else
44 #define CONFIG_SYS_TEXT_BASE 0x0FF80000
45 #define SH7785LCR_SDRAM_BASE (0x08000000)
46 #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
47 #define SH7785LCR_FLASH_BASE_1 (0xa0000000)
48 #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
49 #define SH7785LCR_USB_BASE (0xb4000000)
50 #endif
51
52 #define CONFIG_SYS_LONGHELP
53 #define CONFIG_SYS_CBSIZE 256
54 #define CONFIG_SYS_PBSIZE 256
55 #define CONFIG_SYS_MAXARGS 16
56 #define CONFIG_SYS_BARGSIZE 512
57 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
58
59 /* SCIF */
60 #define CONFIG_SCIF_CONSOLE 1
61 #define CONFIG_CONS_SCIF1 1
62 #define CONFIG_SCIF_EXT_CLOCK 1
63
64 #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
65 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
66 (SH7785LCR_SDRAM_SIZE) - \
67 4 * 1024 * 1024)
68 #undef CONFIG_SYS_ALT_MEMTEST
69 #undef CONFIG_SYS_MEMTEST_SCRATCH
70 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
71
72 #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
73 #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
74 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
75
76 #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
77 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
78 #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
79 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
80
81 /* FLASH */
82 #define CONFIG_FLASH_CFI_DRIVER
83 #define CONFIG_SYS_FLASH_CFI
84 #undef CONFIG_SYS_FLASH_QUIET_TEST
85 #define CONFIG_SYS_FLASH_EMPTY_INFO
86 #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
87 #define CONFIG_SYS_MAX_FLASH_SECT 512
88
89 #define CONFIG_SYS_MAX_FLASH_BANKS 1
90 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
91 (0 * SH7785LCR_FLASH_BANK_SIZE) }
92
93 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
94 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
95 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
96 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
97
98 #undef CONFIG_SYS_FLASH_PROTECTION
99 #undef CONFIG_SYS_DIRECT_FLASH_TFTP
100
101 /* R8A66597 */
102 #define CONFIG_USB_R8A66597_HCD
103 #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
104 #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
105 #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
106 #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
107
108 /* PCI Controller */
109 #define CONFIG_PCI
110 #define CONFIG_SH4_PCI
111 #define CONFIG_SH7780_PCI
112 #if defined(CONFIG_SH_32BIT)
113 #define CONFIG_SH7780_PCI_LSR 0x1ff00001
114 #define CONFIG_SH7780_PCI_LAR 0x5f000000
115 #define CONFIG_SH7780_PCI_BAR 0x5f000000
116 #else
117 #define CONFIG_SH7780_PCI_LSR 0x07f00001
118 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
119 #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
120 #endif
121 #define CONFIG_PCI_PNP
122 #define CONFIG_PCI_SCAN_SHOW 1
123
124 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
125 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
126 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
127
128 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
129 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
130 #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
131
132 #if defined(CONFIG_SH_32BIT)
133 #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
134 #else
135 #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
136 #endif
137 #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
138 #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
139
140 /* ENV setting */
141 #define CONFIG_ENV_IS_IN_FLASH
142 #define CONFIG_ENV_OVERWRITE 1
143 #define CONFIG_ENV_SECT_SIZE (256 * 1024)
144 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
145 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
146 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
147 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
148
149 /* Board Clock */
150 /* The SCIF used external clock. system clock only used timer. */
151 #define CONFIG_SYS_CLK_FREQ 50000000
152 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
153 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
154 #define CONFIG_SYS_TMU_CLK_DIV 4
155
156 #endif /* __SH7785LCR_H */