include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9 /* Virtual target or real hardware */
  10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  11
  12 /*
  13  * High level configuration
  14  */
  15 #define CONFIG_DISPLAY_BOARDINFO_LATE
  16 #define CONFIG_CLOCKS
  17
  18 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  19
  20 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  21
  22 /* add target to build it automatically upon "make" */
  23 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  24
  25 /*
  26  * Memory configurations
  27  */
  28 #define CONFIG_NR_DRAM_BANKS            1
  29 #define PHYS_SDRAM_1                    0x0
  30 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  31 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  32 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  33 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  34 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  35 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  36 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  37 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFE00000
  38 #define CONFIG_SYS_INIT_RAM_SIZE        0x40000 /* 256KB */
  39 #endif
  40 #define CONFIG_SYS_INIT_SP_OFFSET               \
  41         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  42 #define CONFIG_SYS_INIT_SP_ADDR                 \
  43         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  44
  45 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  47 #define CONFIG_SYS_TEXT_BASE            0x08000040
  48 #else
  49 #define CONFIG_SYS_TEXT_BASE            0x01000040
  50 #endif
  51
  52 /*
  53  * U-Boot general configurations
  54  */
  55 #define CONFIG_SYS_LONGHELP
  56 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  57 #define CONFIG_SYS_PBSIZE       \
  58         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  59                                                 /* Print buffer size */
  60 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  61 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  62                                                 /* Boot argument buffer size */
  63 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  64 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  65
  66 #ifndef CONFIG_SYS_HOSTNAME
  67 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  68 #endif
  69
  70 #define CONFIG_CMD_PXE
  71 #define CONFIG_MENU
  72
  73 /*
  74  * Cache
  75  */
  76 #define CONFIG_SYS_L2_PL310
  77 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  78
  79 /*
  80  * EPCS/EPCQx1 Serial Flash Controller
  81  */
  82 #ifdef CONFIG_ALTERA_SPI
  83 #define CONFIG_SF_DEFAULT_SPEED         30000000
  84 /*
  85  * The base address is configurable in QSys, each board must specify the
  86  * base address based on it's particular FPGA configuration. Please note
  87  * that the address here is incremented by  0x400  from the Base address
  88  * selected in QSys, since the SPI registers are at offset +0x400.
  89  * #define CONFIG_SYS_SPI_BASE          0xff240400
  90  */
  91 #endif
  92
  93 /*
  94  * Ethernet on SoC (EMAC)
  95  */
  96 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  97 #define CONFIG_DW_ALTDESCRIPTOR
  98 #define CONFIG_MII
  99 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 100 #endif
 101
 102 /*
 103  * FPGA Driver
 104  */
 105 #ifdef CONFIG_CMD_FPGA
 106 #define CONFIG_FPGA_COUNT               1
 107 #endif
 108
 109 /*
 110  * L4 OSC1 Timer 0
 111  */
 112 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 113 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 114 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 115 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 116 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 117 #define CONFIG_SYS_TIMER_RATE           2400000
 118 #else
 119 #define CONFIG_SYS_TIMER_RATE           25000000
 120 #endif
 121
 122 /*
 123  * L4 Watchdog
 124  */
 125 #ifdef CONFIG_HW_WATCHDOG
 126 #define CONFIG_DESIGNWARE_WATCHDOG
 127 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 128 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 129 #define CONFIG_WATCHDOG_TIMEOUT_MSECS   30000
 130 #endif
 131
 132 /*
 133  * MMC Driver
 134  */
 135 #ifdef CONFIG_CMD_MMC
 136 #define CONFIG_BOUNCE_BUFFER
 137 /* FIXME */
 138 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 139 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 140 #endif
 141
 142 /*
 143  * NAND Support
 144  */
 145 #ifdef CONFIG_NAND_DENALI
 146 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 147 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 148 #define CONFIG_SYS_NAND_ONFI_DETECTION
 149 #define CONFIG_NAND_DENALI_ECC_SIZE     512
 150 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 151 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 152 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 153 #endif
 154
 155 /*
 156  * I2C support
 157  */
 158 #define CONFIG_SYS_I2C
 159 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 160 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 161 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 162 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 163 /* Using standard mode which the speed up to 100Kb/s */
 164 #define CONFIG_SYS_I2C_SPEED            100000
 165 #define CONFIG_SYS_I2C_SPEED1           100000
 166 #define CONFIG_SYS_I2C_SPEED2           100000
 167 #define CONFIG_SYS_I2C_SPEED3           100000
 168 /* Address of device when used as slave */
 169 #define CONFIG_SYS_I2C_SLAVE            0x02
 170 #define CONFIG_SYS_I2C_SLAVE1           0x02
 171 #define CONFIG_SYS_I2C_SLAVE2           0x02
 172 #define CONFIG_SYS_I2C_SLAVE3           0x02
 173 #ifndef __ASSEMBLY__
 174 /* Clock supplied to I2C controller in unit of MHz */
 175 unsigned int cm_get_l4_sp_clk_hz(void);
 176 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 177 #endif
 178
 179 /*
 180  * QSPI support
 181  */
 182 /* Enable multiple SPI NOR flash manufacturers */
 183 #ifndef CONFIG_SPL_BUILD
 184 #define CONFIG_SPI_FLASH_MTD
 185 #define CONFIG_MTD_DEVICE
 186 #define CONFIG_MTD_PARTITIONS
 187 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 188 #endif
 189 /* QSPI reference clock */
 190 #ifndef __ASSEMBLY__
 191 unsigned int cm_get_qspi_controller_clk_hz(void);
 192 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 193 #endif
 194 #define CONFIG_CQSPI_DECODER            0
 195 #define CONFIG_BOUNCE_BUFFER
 196
 197 /*
 198  * Designware SPI support
 199  */
 200
 201 /*
 202  * Serial Driver
 203  */
 204 #define CONFIG_SYS_NS16550_SERIAL
 205 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 206 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 207 #define CONFIG_SYS_NS16550_CLK          1000000
 208 #elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
 209 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 210 #define CONFIG_SYS_NS16550_CLK          100000000
 211 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 212 #define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
 213 #define CONFIG_SYS_NS16550_CLK          50000000
 214 #endif
 215 #define CONFIG_CONS_INDEX               1
 216
 217 /*
 218  * USB
 219  */
 220
 221 /*
 222  * USB Gadget (DFU, UMS)
 223  */
 224 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 225 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 226
 227 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (16 * 1024 * 1024)
 228 #define DFU_DEFAULT_POLL_TIMEOUT        300
 229
 230 /* USB IDs */
 231 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 232 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 233 #endif
 234
 235 /*
 236  * U-Boot environment
 237  */
 238 #if !defined(CONFIG_ENV_SIZE)
 239 #define CONFIG_ENV_SIZE                 (8 * 1024)
 240 #endif
 241
 242 /* Environment for SDMMC boot */
 243 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 244 #define CONFIG_SYS_MMC_ENV_DEV          0 /* device 0 */
 245 #define CONFIG_ENV_OFFSET               (34 * 512) /* just after the GPT */
 246 #endif
 247
 248 /* Environment for QSPI boot */
 249 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 250 #define CONFIG_ENV_OFFSET               0x00100000
 251 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 252 #endif
 253
 254 /*
 255  * mtd partitioning for serial NOR flash
 256  *
 257  * device nor0 <ff705000.spi.0>, # parts = 6
 258  * #: name                size            offset          mask_flags
 259  * 0: u-boot              0x00100000      0x00000000      0
 260  * 1: env1                0x00040000      0x00100000      0
 261  * 2: env2                0x00040000      0x00140000      0
 262  * 3: UBI                 0x03e80000      0x00180000      0
 263  * 4: boot                0x00e80000      0x00180000      0
 264  * 5: rootfs              0x01000000      0x01000000      0
 265  *
 266  */
 267 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 268 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 269                                 "1m(u-boot),"           \
 270                                 "256k(env1),"           \
 271                                 "256k(env2),"           \
 272                                 "14848k(boot),"         \
 273                                 "16m(rootfs),"          \
 274                                 "-@1536k(UBI)\0"
 275 #endif
 276
 277 /*
 278  * SPL
 279  *
 280  * SRAM Memory layout:
 281  *
 282  * 0xFFFF_0000 ...... Start of SRAM
 283  * 0xFFFF_xxxx ...... Top of stack (grows down)
 284  * 0xFFFF_yyyy ...... Malloc area
 285  * 0xFFFF_zzzz ...... Global Data
 286  * 0xFFFF_FF00 ...... End of SRAM
 287  */
 288 #define CONFIG_SPL_FRAMEWORK
 289 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 290 #define CONFIG_SPL_MAX_SIZE             CONFIG_SYS_INIT_RAM_SIZE
 291
 292 /* SPL SDMMC boot support */
 293 #ifdef CONFIG_SPL_MMC_SUPPORT
 294 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 295 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 296 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 297 #endif
 298 #else
 299 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
 300 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 301 #endif
 302 #endif
 303
 304 /* SPL QSPI boot support */
 305 #ifdef CONFIG_SPL_SPI_SUPPORT
 306 #define CONFIG_SPL_SPI_LOAD
 307 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 308 #endif
 309
 310 /* SPL NAND boot support */
 311 #ifdef CONFIG_SPL_NAND_SUPPORT
 312 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 313 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 314 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 315 #endif
 316
 317 /*
 318  * Stack setup
 319  */
 320 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 321
 322 /* Extra Environment */
 323 #ifndef CONFIG_SPL_BUILD
 324 #include <config_distro_defaults.h>
 325
 326 #ifdef CONFIG_CMD_PXE
 327 #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
 328 #else
 329 #define BOOT_TARGET_DEVICES_PXE(func)
 330 #endif
 331
 332 #ifdef CONFIG_CMD_MMC
 333 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 334 #else
 335 #define BOOT_TARGET_DEVICES_MMC(func)
 336 #endif
 337
 338 #define BOOT_TARGET_DEVICES(func) \
 339         BOOT_TARGET_DEVICES_MMC(func) \
 340         BOOT_TARGET_DEVICES_PXE(func) \
 341         func(DHCP, dhcp, na)
 342
 343 #include <config_distro_bootcmd.h>
 344
 345 #ifndef CONFIG_EXTRA_ENV_SETTINGS
 346 #define CONFIG_EXTRA_ENV_SETTINGS \
 347         "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 348         "bootm_size=0xa000000\0" \
 349         "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
 350         "fdt_addr_r=0x02000000\0" \
 351         "scriptaddr=0x02100000\0" \
 352         "pxefile_addr_r=0x02200000\0" \
 353         "ramdisk_addr_r=0x02300000\0" \
 354         BOOTENV
 355
 356 #endif
 357 #endif
 358
 359 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */