include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
   7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
   8
   9
  10 /* Virtual target or real hardware */
  11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  12
  13 #define CONFIG_SYS_THUMB_BUILD
  14
  15 /*
  16  * High level configuration
  17  */
  18 #define CONFIG_DISPLAY_CPUINFO
  19 #define CONFIG_DISPLAY_BOARDINFO_LATE
  20 #define CONFIG_ARCH_MISC_INIT
  21 #define CONFIG_ARCH_EARLY_INIT_R
  22 #define CONFIG_SYS_NO_FLASH
  23 #define CONFIG_CLOCKS
  24
  25 #define CONFIG_CRC32_VERIFY
  26
  27 #define CONFIG_FIT
  28 #define CONFIG_OF_LIBFDT
  29 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  30
  31 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  32
  33 /*
  34  * Memory configurations
  35  */
  36 #define CONFIG_NR_DRAM_BANKS            1
  37 #define PHYS_SDRAM_1                    0x0
  38 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  39 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  40 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  41
  42 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  43 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  44 #define CONFIG_SYS_INIT_SP_OFFSET               \
  45         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  46 #define CONFIG_SYS_INIT_SP_ADDR                 \
  47         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  48
  49 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  50 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  51 #define CONFIG_SYS_TEXT_BASE            0x08000040
  52 #else
  53 #define CONFIG_SYS_TEXT_BASE            0x01000040
  54 #endif
  55
  56 /*
  57  * U-Boot general configurations
  58  */
  59 #define CONFIG_SYS_LONGHELP
  60 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  61 #define CONFIG_SYS_PBSIZE       \
  62         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  63                                                 /* Print buffer size */
  64 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  65 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  66                                                 /* Boot argument buffer size */
  67 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
  68 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  69 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  70 #define CONFIG_SYS_HUSH_PARSER
  71
  72 /*
  73  * Cache
  74  */
  75 #define CONFIG_SYS_CACHELINE_SIZE 32
  76 #define CONFIG_SYS_L2_PL310
  77 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  78
  79 /*
  80  * SDRAM controller
  81  */
  82 #define CONFIG_ALTERA_SDRAM
  83
  84 /*
  85  * EPCS/EPCQx1 Serial Flash Controller
  86  */
  87 #ifdef CONFIG_ALTERA_SPI
  88 #define CONFIG_CMD_SPI
  89 #define CONFIG_CMD_SF
  90 #define CONFIG_SF_DEFAULT_SPEED         30000000
  91 #define CONFIG_SPI_FLASH_BAR
  92 /*
  93  * The base address is configurable in QSys, each board must specify the
  94  * base address based on it's particular FPGA configuration. Please note
  95  * that the address here is incremented by  0x400  from the Base address
  96  * selected in QSys, since the SPI registers are at offset +0x400.
  97  * #define CONFIG_SYS_SPI_BASE          0xff240400
  98  */
  99 #endif
 100
 101 /*
 102  * Ethernet on SoC (EMAC)
 103  */
 104 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 105 #define CONFIG_DW_ALTDESCRIPTOR
 106 #define CONFIG_MII
 107 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 108 #define CONFIG_PHYLIB
 109 #define CONFIG_PHY_GIGE
 110 #endif
 111
 112 /*
 113  * FPGA Driver
 114  */
 115 #ifdef CONFIG_CMD_FPGA
 116 #define CONFIG_FPGA
 117 #define CONFIG_FPGA_ALTERA
 118 #define CONFIG_FPGA_SOCFPGA
 119 #define CONFIG_FPGA_COUNT               1
 120 #endif
 121
 122 /*
 123  * L4 OSC1 Timer 0
 124  */
 125 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 126 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 127 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 128 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 129 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 130 #define CONFIG_SYS_TIMER_RATE           2400000
 131 #else
 132 #define CONFIG_SYS_TIMER_RATE           25000000
 133 #endif
 134
 135 /*
 136  * L4 Watchdog
 137  */
 138 #ifdef CONFIG_HW_WATCHDOG
 139 #define CONFIG_DESIGNWARE_WATCHDOG
 140 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 141 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 142 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 143 #endif
 144
 145 /*
 146  * MMC Driver
 147  */
 148 #ifdef CONFIG_CMD_MMC
 149 #define CONFIG_MMC
 150 #define CONFIG_BOUNCE_BUFFER
 151 #define CONFIG_GENERIC_MMC
 152 #define CONFIG_DWMMC
 153 #define CONFIG_SOCFPGA_DWMMC
 154 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
 155 #define CONFIG_SOCFPGA_DWMMC_DRVSEL     3
 156 #define CONFIG_SOCFPGA_DWMMC_SMPSEL     0
 157 /* FIXME */
 158 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 159 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 160 #endif
 161
 162 /*
 163  * I2C support
 164  */
 165 #define CONFIG_SYS_I2C
 166 #define CONFIG_SYS_I2C_DW
 167 #define CONFIG_SYS_I2C_BUS_MAX          4
 168 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 169 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 170 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 171 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 172 /* Using standard mode which the speed up to 100Kb/s */
 173 #define CONFIG_SYS_I2C_SPEED            100000
 174 #define CONFIG_SYS_I2C_SPEED1           100000
 175 #define CONFIG_SYS_I2C_SPEED2           100000
 176 #define CONFIG_SYS_I2C_SPEED3           100000
 177 /* Address of device when used as slave */
 178 #define CONFIG_SYS_I2C_SLAVE            0x02
 179 #define CONFIG_SYS_I2C_SLAVE1           0x02
 180 #define CONFIG_SYS_I2C_SLAVE2           0x02
 181 #define CONFIG_SYS_I2C_SLAVE3           0x02
 182 #ifndef __ASSEMBLY__
 183 /* Clock supplied to I2C controller in unit of MHz */
 184 unsigned int cm_get_l4_sp_clk_hz(void);
 185 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 186 #endif
 187 #define CONFIG_CMD_I2C
 188
 189 /*
 190  * QSPI support
 191  */
 192 /* Enable multiple SPI NOR flash manufacturers */
 193 #ifndef CONFIG_SPL_BUILD
 194 #define CONFIG_SPI_FLASH_MTD
 195 #define CONFIG_CMD_MTDPARTS
 196 #define CONFIG_MTD_DEVICE
 197 #define CONFIG_MTD_PARTITIONS
 198 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi"
 199 #endif
 200 /* QSPI reference clock */
 201 #ifndef __ASSEMBLY__
 202 unsigned int cm_get_qspi_controller_clk_hz(void);
 203 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 204 #endif
 205 #define CONFIG_CQSPI_DECODER            0
 206 #define CONFIG_CMD_SF
 207 #define CONFIG_SPI_FLASH_BAR
 208
 209 /*
 210  * Designware SPI support
 211  */
 212 #define CONFIG_CMD_SPI
 213
 214 /*
 215  * Serial Driver
 216  */
 217 #define CONFIG_SYS_NS16550_SERIAL
 218 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 219 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 220 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 221 #define CONFIG_SYS_NS16550_CLK          1000000
 222 #else
 223 #define CONFIG_SYS_NS16550_CLK          100000000
 224 #endif
 225 #define CONFIG_CONS_INDEX               1
 226 #define CONFIG_BAUDRATE                 115200
 227
 228 /*
 229  * USB
 230  */
 231 #ifdef CONFIG_CMD_USB
 232 #define CONFIG_USB_DWC2
 233 #define CONFIG_USB_STORAGE
 234 /*
 235  * NOTE: User must define either of the following to select which
 236  *       of the two USB controllers available on SoCFPGA to use.
 237  *       The DWC2 driver doesn't support multiple USB controllers.
 238  * #define CONFIG_USB_DWC2_REG_ADDR     SOCFPGA_USB0_ADDRESS
 239  * #define CONFIG_USB_DWC2_REG_ADDR     SOCFPGA_USB1_ADDRESS
 240  */
 241 #endif
 242
 243 /*
 244  * USB Gadget (DFU, UMS)
 245  */
 246 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 247 #define CONFIG_USB_GADGET
 248 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 249 #define CONFIG_USB_GADGET_DUALSPEED
 250 #define CONFIG_USB_GADGET_VBUS_DRAW     2
 251
 252 /* USB Composite download gadget - g_dnl */
 253 #define CONFIG_USB_GADGET_DOWNLOAD
 254 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 255
 256 #define CONFIG_USB_FUNCTION_DFU
 257 #define CONFIG_DFU_MMC
 258 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 259 #define DFU_DEFAULT_POLL_TIMEOUT        300
 260
 261 /* USB IDs */
 262 #define CONFIG_G_DNL_VENDOR_NUM         0x0525  /* NetChip */
 263 #define CONFIG_G_DNL_PRODUCT_NUM        0xA4A5  /* Linux-USB File-backed Storage Gadget */
 264 #define CONFIG_G_DNL_UMS_VENDOR_NUM     CONFIG_G_DNL_VENDOR_NUM
 265 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    CONFIG_G_DNL_PRODUCT_NUM
 266 #ifndef CONFIG_G_DNL_MANUFACTURER
 267 #define CONFIG_G_DNL_MANUFACTURER       "Altera"
 268 #endif
 269 #endif
 270
 271 /*
 272  * U-Boot environment
 273  */
 274 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 275 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 276 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 277 #define CONFIG_ENV_SIZE                 4096
 278
 279 /*
 280  * SPL
 281  *
 282  * SRAM Memory layout:
 283  *
 284  * 0xFFFF_0000 ...... Start of SRAM
 285  * 0xFFFF_xxxx ...... Top of stack (grows down)
 286  * 0xFFFF_yyyy ...... Malloc area
 287  * 0xFFFF_zzzz ...... Global Data
 288  * 0xFFFF_FF00 ...... End of SRAM
 289  */
 290 #define CONFIG_SPL_FRAMEWORK
 291 #define CONFIG_SPL_RAM_DEVICE
 292 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 293 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 294 #ifdef CONFIG_SPL_BUILD
 295 #define CONFIG_SYS_MALLOC_SIMPLE
 296 #endif
 297
 298 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 299 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 300 #define CONFIG_SPL_WATCHDOG_SUPPORT
 301 #define CONFIG_SPL_SERIAL_SUPPORT
 302 #define CONFIG_SPL_MMC_SUPPORT
 303 #define CONFIG_SPL_SPI_SUPPORT
 304
 305 /* SPL SDMMC boot support */
 306 #ifdef CONFIG_SPL_MMC_SUPPORT
 307 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 308 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 309 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 310 #define CONFIG_SPL_LIBDISK_SUPPORT
 311 #else
 312 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      3
 313 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
 314 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      800 /* 400 KB */
 315 #endif
 316 #endif
 317
 318 /* SPL QSPI boot support */
 319 #ifdef CONFIG_SPL_SPI_SUPPORT
 320 #define CONFIG_DM_SEQ_ALIAS             1
 321 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 322 #define CONFIG_SPL_SPI_LOAD
 323 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 324 #endif
 325
 326 /*
 327  * Stack setup
 328  */
 329 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 330
 331 #endif  /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */