include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
   7 #define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
   8
   9
  10 /* Virtual target or real hardware */
  11 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  12
  13 #define CONFIG_SYS_THUMB_BUILD
  14
  15 /*
  16  * High level configuration
  17  */
  18 #define CONFIG_DISPLAY_CPUINFO
  19 #define CONFIG_DISPLAY_BOARDINFO_LATE
  20 #define CONFIG_ARCH_MISC_INIT
  21 #define CONFIG_ARCH_EARLY_INIT_R
  22 #define CONFIG_SYS_NO_FLASH
  23 #define CONFIG_CLOCKS
  24
  25 #define CONFIG_CRC32_VERIFY
  26
  27 #define CONFIG_FIT
  28 #define CONFIG_OF_LIBFDT
  29 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  30
  31 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  32
  33 /*
  34  * Memory configurations
  35  */
  36 #define CONFIG_NR_DRAM_BANKS            1
  37 #define PHYS_SDRAM_1                    0x0
  38 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  39 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  40 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  41
  42 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  43 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  44 #define CONFIG_SYS_INIT_SP_OFFSET               \
  45         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  46 #define CONFIG_SYS_INIT_SP_ADDR                 \
  47         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  48
  49 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  50 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  51 #define CONFIG_SYS_TEXT_BASE            0x08000040
  52 #else
  53 #define CONFIG_SYS_TEXT_BASE            0x01000040
  54 #endif
  55
  56 /*
  57  * U-Boot general configurations
  58  */
  59 #define CONFIG_SYS_LONGHELP
  60 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  61 #define CONFIG_SYS_PBSIZE       \
  62         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  63                                                 /* Print buffer size */
  64 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  65 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  66                                                 /* Boot argument buffer size */
  67 #define CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
  68 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  69 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  70 #define CONFIG_SYS_HUSH_PARSER
  71
  72 /*
  73  * Cache
  74  */
  75 #define CONFIG_SYS_CACHELINE_SIZE 32
  76 #define CONFIG_SYS_L2_PL310
  77 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  78
  79 /*
  80  * SDRAM controller
  81  */
  82 #define CONFIG_ALTERA_SDRAM
  83
  84 /*
  85  * EPCS/EPCQx1 Serial Flash Controller
  86  */
  87 #ifdef CONFIG_ALTERA_SPI
  88 #define CONFIG_CMD_SPI
  89 #define CONFIG_CMD_SF
  90 #define CONFIG_SF_DEFAULT_SPEED         30000000
  91 #define CONFIG_SPI_FLASH_STMICRO
  92 #define CONFIG_SPI_FLASH_BAR
  93 /*
  94  * The base address is configurable in QSys, each board must specify the
  95  * base address based on it's particular FPGA configuration. Please note
  96  * that the address here is incremented by  0x400  from the Base address
  97  * selected in QSys, since the SPI registers are at offset +0x400.
  98  * #define CONFIG_SYS_SPI_BASE          0xff240400
  99  */
 100 #endif
 101
 102 /*
 103  * Ethernet on SoC (EMAC)
 104  */
 105 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 106 #define CONFIG_DW_ALTDESCRIPTOR
 107 #define CONFIG_MII
 108 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 109 #define CONFIG_PHYLIB
 110 #define CONFIG_PHY_GIGE
 111 #endif
 112
 113 /*
 114  * FPGA Driver
 115  */
 116 #ifdef CONFIG_CMD_FPGA
 117 #define CONFIG_FPGA
 118 #define CONFIG_FPGA_ALTERA
 119 #define CONFIG_FPGA_SOCFPGA
 120 #define CONFIG_FPGA_COUNT               1
 121 #endif
 122
 123 /*
 124  * L4 OSC1 Timer 0
 125  */
 126 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 127 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 128 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 129 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 130 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 131 #define CONFIG_SYS_TIMER_RATE           2400000
 132 #else
 133 #define CONFIG_SYS_TIMER_RATE           25000000
 134 #endif
 135
 136 /*
 137  * L4 Watchdog
 138  */
 139 #ifdef CONFIG_HW_WATCHDOG
 140 #define CONFIG_DESIGNWARE_WATCHDOG
 141 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 142 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 143 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 144 #endif
 145
 146 /*
 147  * MMC Driver
 148  */
 149 #ifdef CONFIG_CMD_MMC
 150 #define CONFIG_MMC
 151 #define CONFIG_BOUNCE_BUFFER
 152 #define CONFIG_GENERIC_MMC
 153 #define CONFIG_DWMMC
 154 #define CONFIG_SOCFPGA_DWMMC
 155 #define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH 1024
 156 #define CONFIG_SOCFPGA_DWMMC_DRVSEL     3
 157 #define CONFIG_SOCFPGA_DWMMC_SMPSEL     0
 158 /* FIXME */
 159 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 160 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 161 #endif
 162
 163 /*
 164  * I2C support
 165  */
 166 #define CONFIG_SYS_I2C
 167 #define CONFIG_SYS_I2C_DW
 168 #define CONFIG_SYS_I2C_BUS_MAX          4
 169 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 170 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 171 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 172 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 173 /* Using standard mode which the speed up to 100Kb/s */
 174 #define CONFIG_SYS_I2C_SPEED            100000
 175 #define CONFIG_SYS_I2C_SPEED1           100000
 176 #define CONFIG_SYS_I2C_SPEED2           100000
 177 #define CONFIG_SYS_I2C_SPEED3           100000
 178 /* Address of device when used as slave */
 179 #define CONFIG_SYS_I2C_SLAVE            0x02
 180 #define CONFIG_SYS_I2C_SLAVE1           0x02
 181 #define CONFIG_SYS_I2C_SLAVE2           0x02
 182 #define CONFIG_SYS_I2C_SLAVE3           0x02
 183 #ifndef __ASSEMBLY__
 184 /* Clock supplied to I2C controller in unit of MHz */
 185 unsigned int cm_get_l4_sp_clk_hz(void);
 186 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 187 #endif
 188 #define CONFIG_CMD_I2C
 189
 190 /*
 191  * QSPI support
 192  */
 193 /* Enable multiple SPI NOR flash manufacturers */
 194 #define CONFIG_SPI_FLASH_STMICRO        /* Micron/Numonyx flash */
 195 #define CONFIG_SPI_FLASH_SPANSION       /* Spansion flash */
 196 #ifndef CONFIG_SPL_BUILD
 197 #define CONFIG_SPI_FLASH_MTD
 198 #define CONFIG_CMD_MTDPARTS
 199 #define CONFIG_MTD_DEVICE
 200 #define CONFIG_MTD_PARTITIONS
 201 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi"
 202 #endif
 203 /* QSPI reference clock */
 204 #ifndef __ASSEMBLY__
 205 unsigned int cm_get_qspi_controller_clk_hz(void);
 206 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 207 #endif
 208 #define CONFIG_CQSPI_DECODER            0
 209 #define CONFIG_CMD_SF
 210 #define CONFIG_SPI_FLASH_BAR
 211
 212 /*
 213  * Designware SPI support
 214  */
 215 #define CONFIG_CMD_SPI
 216
 217 /*
 218  * Serial Driver
 219  */
 220 #define CONFIG_SYS_NS16550_SERIAL
 221 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 222 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 223 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 224 #define CONFIG_SYS_NS16550_CLK          1000000
 225 #else
 226 #define CONFIG_SYS_NS16550_CLK          100000000
 227 #endif
 228 #define CONFIG_CONS_INDEX               1
 229 #define CONFIG_BAUDRATE                 115200
 230
 231 /*
 232  * USB
 233  */
 234 #ifdef CONFIG_CMD_USB
 235 #define CONFIG_USB_DWC2
 236 #define CONFIG_USB_STORAGE
 237 /*
 238  * NOTE: User must define either of the following to select which
 239  *       of the two USB controllers available on SoCFPGA to use.
 240  *       The DWC2 driver doesn't support multiple USB controllers.
 241  * #define CONFIG_USB_DWC2_REG_ADDR     SOCFPGA_USB0_ADDRESS
 242  * #define CONFIG_USB_DWC2_REG_ADDR     SOCFPGA_USB1_ADDRESS
 243  */
 244 #endif
 245
 246 /*
 247  * USB Gadget (DFU, UMS)
 248  */
 249 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 250 #define CONFIG_USB_GADGET
 251 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 252 #define CONFIG_USB_GADGET_DUALSPEED
 253 #define CONFIG_USB_GADGET_VBUS_DRAW     2
 254
 255 /* USB Composite download gadget - g_dnl */
 256 #define CONFIG_USB_GADGET_DOWNLOAD
 257 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 258
 259 #define CONFIG_USB_FUNCTION_DFU
 260 #define CONFIG_DFU_MMC
 261 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 262 #define DFU_DEFAULT_POLL_TIMEOUT        300
 263
 264 /* USB IDs */
 265 #define CONFIG_G_DNL_VENDOR_NUM         0x0525  /* NetChip */
 266 #define CONFIG_G_DNL_PRODUCT_NUM        0xA4A5  /* Linux-USB File-backed Storage Gadget */
 267 #define CONFIG_G_DNL_UMS_VENDOR_NUM     CONFIG_G_DNL_VENDOR_NUM
 268 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    CONFIG_G_DNL_PRODUCT_NUM
 269 #ifndef CONFIG_G_DNL_MANUFACTURER
 270 #define CONFIG_G_DNL_MANUFACTURER       "Altera"
 271 #endif
 272 #endif
 273
 274 /*
 275  * U-Boot environment
 276  */
 277 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 278 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 279 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 280 #define CONFIG_ENV_SIZE                 4096
 281
 282 /*
 283  * SPL
 284  *
 285  * SRAM Memory layout:
 286  *
 287  * 0xFFFF_0000 ...... Start of SRAM
 288  * 0xFFFF_xxxx ...... Top of stack (grows down)
 289  * 0xFFFF_yyyy ...... Malloc area
 290  * 0xFFFF_zzzz ...... Global Data
 291  * 0xFFFF_FF00 ...... End of SRAM
 292  */
 293 #define CONFIG_SPL_FRAMEWORK
 294 #define CONFIG_SPL_RAM_DEVICE
 295 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 296 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 297 #ifdef CONFIG_SPL_BUILD
 298 #define CONFIG_SYS_MALLOC_SIMPLE
 299 #endif
 300
 301 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 302 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 303 #define CONFIG_SPL_WATCHDOG_SUPPORT
 304 #define CONFIG_SPL_SERIAL_SUPPORT
 305 #define CONFIG_SPL_MMC_SUPPORT
 306 #define CONFIG_SPL_SPI_SUPPORT
 307
 308 /* SPL SDMMC boot support */
 309 #ifdef CONFIG_SPL_MMC_SUPPORT
 310 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 311 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 312 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 313 #define CONFIG_SPL_LIBDISK_SUPPORT
 314 #else
 315 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      3
 316 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
 317 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      800 /* 400 KB */
 318 #endif
 319 #endif
 320
 321 /* SPL QSPI boot support */
 322 #ifdef CONFIG_SPL_SPI_SUPPORT
 323 #define CONFIG_DM_SEQ_ALIAS             1
 324 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 325 #define CONFIG_SPL_SPI_LOAD
 326 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 327 #endif
 328
 329 /*
 330  * Stack setup
 331  */
 332 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 333
 334 #endif  /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */