include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9 /* Virtual target or real hardware */
  10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  11
  12 #define CONFIG_SYS_THUMB_BUILD
  13
  14 /*
  15  * High level configuration
  16  */
  17 #define CONFIG_DISPLAY_BOARDINFO_LATE
  18 #define CONFIG_ARCH_MISC_INIT
  19 #define CONFIG_ARCH_EARLY_INIT_R
  20 #define CONFIG_SYS_NO_FLASH
  21 #define CONFIG_CLOCKS
  22
  23 #define CONFIG_CRC32_VERIFY
  24
  25 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  26
  27 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  28
  29 /* add target to build it automatically upon "make" */
  30 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  31
  32 /*
  33  * Memory configurations
  34  */
  35 #define CONFIG_NR_DRAM_BANKS            1
  36 #define PHYS_SDRAM_1                    0x0
  37 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  38 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  39 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  40
  41 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  42 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  43 #define CONFIG_SYS_INIT_SP_OFFSET               \
  44         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  45 #define CONFIG_SYS_INIT_SP_ADDR                 \
  46         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  47
  48 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  49 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  50 #define CONFIG_SYS_TEXT_BASE            0x08000040
  51 #else
  52 #define CONFIG_SYS_TEXT_BASE            0x01000040
  53 #endif
  54
  55 /*
  56  * U-Boot general configurations
  57  */
  58 #define CONFIG_SYS_LONGHELP
  59 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  60 #define CONFIG_SYS_PBSIZE       \
  61         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  62                                                 /* Print buffer size */
  63 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  64 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  65                                                 /* Boot argument buffer size */
  66 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  67 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  68
  69 #ifndef CONFIG_SYS_HOSTNAME
  70 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  71 #endif
  72
  73 /*
  74  * Cache
  75  */
  76 #define CONFIG_SYS_L2_PL310
  77 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  78
  79 /*
  80  * SDRAM controller
  81  */
  82 #define CONFIG_ALTERA_SDRAM
  83
  84 /*
  85  * EPCS/EPCQx1 Serial Flash Controller
  86  */
  87 #ifdef CONFIG_ALTERA_SPI
  88 #define CONFIG_SF_DEFAULT_SPEED         30000000
  89 /*
  90  * The base address is configurable in QSys, each board must specify the
  91  * base address based on it's particular FPGA configuration. Please note
  92  * that the address here is incremented by  0x400  from the Base address
  93  * selected in QSys, since the SPI registers are at offset +0x400.
  94  * #define CONFIG_SYS_SPI_BASE          0xff240400
  95  */
  96 #endif
  97
  98 /*
  99  * Ethernet on SoC (EMAC)
 100  */
 101 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 102 #define CONFIG_DW_ALTDESCRIPTOR
 103 #define CONFIG_MII
 104 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 105 #define CONFIG_PHY_GIGE
 106 #endif
 107
 108 /*
 109  * FPGA Driver
 110  */
 111 #ifdef CONFIG_CMD_FPGA
 112 #define CONFIG_FPGA
 113 #define CONFIG_FPGA_ALTERA
 114 #define CONFIG_FPGA_SOCFPGA
 115 #define CONFIG_FPGA_COUNT               1
 116 #endif
 117
 118 /*
 119  * L4 OSC1 Timer 0
 120  */
 121 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 122 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 123 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 124 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 125 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 126 #define CONFIG_SYS_TIMER_RATE           2400000
 127 #else
 128 #define CONFIG_SYS_TIMER_RATE           25000000
 129 #endif
 130
 131 /*
 132  * L4 Watchdog
 133  */
 134 #ifdef CONFIG_HW_WATCHDOG
 135 #define CONFIG_DESIGNWARE_WATCHDOG
 136 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 137 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 138 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 139 #endif
 140
 141 /*
 142  * MMC Driver
 143  */
 144 #ifdef CONFIG_CMD_MMC
 145 #define CONFIG_BOUNCE_BUFFER
 146 #define CONFIG_GENERIC_MMC
 147 /* FIXME */
 148 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 149 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 150 #endif
 151
 152 /*
 153  * NAND Support
 154  */
 155 #ifdef CONFIG_NAND_DENALI
 156 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 157 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 158 #define CONFIG_SYS_NAND_ONFI_DETECTION
 159 #define CONFIG_NAND_DENALI_ECC_SIZE     512
 160 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 161 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 162 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 163 #endif
 164
 165 /*
 166  * I2C support
 167  */
 168 #define CONFIG_SYS_I2C
 169 #define CONFIG_SYS_I2C_BUS_MAX          4
 170 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 171 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 172 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 173 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 174 /* Using standard mode which the speed up to 100Kb/s */
 175 #define CONFIG_SYS_I2C_SPEED            100000
 176 #define CONFIG_SYS_I2C_SPEED1           100000
 177 #define CONFIG_SYS_I2C_SPEED2           100000
 178 #define CONFIG_SYS_I2C_SPEED3           100000
 179 /* Address of device when used as slave */
 180 #define CONFIG_SYS_I2C_SLAVE            0x02
 181 #define CONFIG_SYS_I2C_SLAVE1           0x02
 182 #define CONFIG_SYS_I2C_SLAVE2           0x02
 183 #define CONFIG_SYS_I2C_SLAVE3           0x02
 184 #ifndef __ASSEMBLY__
 185 /* Clock supplied to I2C controller in unit of MHz */
 186 unsigned int cm_get_l4_sp_clk_hz(void);
 187 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 188 #endif
 189
 190 /*
 191  * QSPI support
 192  */
 193 /* Enable multiple SPI NOR flash manufacturers */
 194 #ifndef CONFIG_SPL_BUILD
 195 #define CONFIG_SPI_FLASH_MTD
 196 #define CONFIG_CMD_MTDPARTS
 197 #define CONFIG_MTD_DEVICE
 198 #define CONFIG_MTD_PARTITIONS
 199 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 200 #endif
 201 /* QSPI reference clock */
 202 #ifndef __ASSEMBLY__
 203 unsigned int cm_get_qspi_controller_clk_hz(void);
 204 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 205 #endif
 206 #define CONFIG_CQSPI_DECODER            0
 207 #define CONFIG_BOUNCE_BUFFER
 208
 209 /*
 210  * Designware SPI support
 211  */
 212
 213 /*
 214  * Serial Driver
 215  */
 216 #define CONFIG_SYS_NS16550_SERIAL
 217 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 218 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 219 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 220 #define CONFIG_SYS_NS16550_CLK          1000000
 221 #else
 222 #define CONFIG_SYS_NS16550_CLK          100000000
 223 #endif
 224 #define CONFIG_CONS_INDEX               1
 225 #define CONFIG_BAUDRATE                 115200
 226
 227 /*
 228  * USB
 229  */
 230 #ifdef CONFIG_CMD_USB
 231 #define CONFIG_USB_DWC2
 232 #endif
 233
 234 /*
 235  * USB Gadget (DFU, UMS)
 236  */
 237 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 238 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 239
 240 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 241 #define DFU_DEFAULT_POLL_TIMEOUT        300
 242
 243 /* USB IDs */
 244 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 245 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 246 #endif
 247
 248 /*
 249  * U-Boot environment
 250  */
 251 #if !defined(CONFIG_ENV_SIZE)
 252 #define CONFIG_ENV_SIZE                 4096
 253 #endif
 254
 255 /* Environment for SDMMC boot */
 256 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 257 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
 258 #define CONFIG_ENV_OFFSET               512     /* just after the MBR */
 259 #endif
 260
 261 /* Environment for QSPI boot */
 262 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 263 #define CONFIG_ENV_OFFSET               0x00100000
 264 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 265 #endif
 266
 267 /*
 268  * mtd partitioning for serial NOR flash
 269  *
 270  * device nor0 <ff705000.spi.0>, # parts = 6
 271  * #: name                size            offset          mask_flags
 272  * 0: u-boot              0x00100000      0x00000000      0
 273  * 1: env1                0x00040000      0x00100000      0
 274  * 2: env2                0x00040000      0x00140000      0
 275  * 3: UBI                 0x03e80000      0x00180000      0
 276  * 4: boot                0x00e80000      0x00180000      0
 277  * 5: rootfs              0x01000000      0x01000000      0
 278  *
 279  */
 280 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 281 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 282                                 "1m(u-boot),"           \
 283                                 "256k(env1),"           \
 284                                 "256k(env2),"           \
 285                                 "14848k(boot),"         \
 286                                 "16m(rootfs),"          \
 287                                 "-@1536k(UBI)\0"
 288 #endif
 289
 290 /* UBI and UBIFS support */
 291 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
 292 #define CONFIG_CMD_UBIFS
 293 #define CONFIG_RBTREE
 294 #define CONFIG_LZO
 295 #endif
 296
 297 /*
 298  * SPL
 299  *
 300  * SRAM Memory layout:
 301  *
 302  * 0xFFFF_0000 ...... Start of SRAM
 303  * 0xFFFF_xxxx ...... Top of stack (grows down)
 304  * 0xFFFF_yyyy ...... Malloc area
 305  * 0xFFFF_zzzz ...... Global Data
 306  * 0xFFFF_FF00 ...... End of SRAM
 307  */
 308 #define CONFIG_SPL_FRAMEWORK
 309 #define CONFIG_SPL_RAM_DEVICE
 310 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 311 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 312
 313 /* SPL SDMMC boot support */
 314 #ifdef CONFIG_SPL_MMC_SUPPORT
 315 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 316 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 317 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 318 #else
 319 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION      1
 320 #endif
 321 #endif
 322
 323 /* SPL QSPI boot support */
 324 #ifdef CONFIG_SPL_SPI_SUPPORT
 325 #define CONFIG_SPL_SPI_LOAD
 326 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 327 #endif
 328
 329 /* SPL NAND boot support */
 330 #ifdef CONFIG_SPL_NAND_SUPPORT
 331 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 332 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 333 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 334 #endif
 335
 336 /*
 337  * Stack setup
 338  */
 339 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 340
 341 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */