include/configs/socfpga_cyclone5.h

   1 /*
   2  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
   7 #define __CONFIG_SOCFPGA_CYCLONE5_H__
   8
   9 #include <asm/arch/socfpga_base_addrs.h>
  10 #include "../../board/altera/socfpga/pinmux_config.h"
  11 #include "../../board/altera/socfpga/iocsr_config.h"
  12 #include "../../board/altera/socfpga/pll_config.h"
  13
  14 /* U-Boot Commands */
  15 #define CONFIG_SYS_NO_FLASH
  16 #include <config_cmd_default.h>
  17 #define CONFIG_DOS_PARTITION
  18 #define CONFIG_FAT_WRITE
  19 #define CONFIG_HW_WATCHDOG
  20
  21 #define CONFIG_CMD_ASKENV
  22 #define CONFIG_CMD_BOOTZ
  23 #define CONFIG_CMD_CACHE
  24 #define CONFIG_CMD_DFU
  25 #define CONFIG_CMD_DHCP
  26 #define CONFIG_CMD_EXT4
  27 #define CONFIG_CMD_EXT4_WRITE
  28 #define CONFIG_CMD_FAT
  29 #define CONFIG_CMD_FPGA
  30 #define CONFIG_CMD_FS_GENERIC
  31 #define CONFIG_CMD_GREPENV
  32 #define CONFIG_CMD_MII
  33 #define CONFIG_CMD_MMC
  34 #define CONFIG_CMD_NET
  35 #define CONFIG_CMD_PING
  36 #define CONFIG_CMD_USB
  37 #define CONFIG_CMD_USB_MASS_STORAGE
  38
  39
  40 /* Memory configurations */
  41 #define PHYS_SDRAM_1_SIZE               0x40000000      /* 1GiB on SoCDK */
  42
  43 /* Booting Linux */
  44 #define CONFIG_BOOTDELAY        3
  45 #define CONFIG_BOOTFILE         "zImage"
  46 #define CONFIG_BOOTARGS         "console=ttyS0," __stringify(CONFIG_BAUDRATE)
  47 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  48 #define CONFIG_BOOTCOMMAND      "run ramboot"
  49 #else
  50 #define CONFIG_BOOTCOMMAND      "run mmcload; run mmcboot"
  51 #endif
  52 #define CONFIG_LOADADDR         0x8000
  53 #define CONFIG_SYS_LOAD_ADDR    CONFIG_LOADADDR
  54
  55 /* Ethernet on SoC (EMAC) */
  56 #if defined(CONFIG_CMD_NET)
  57 #define CONFIG_EMAC_BASE                SOCFPGA_EMAC1_ADDRESS
  58 #define CONFIG_PHY_INTERFACE_MODE       PHY_INTERFACE_MODE_RGMII
  59
  60 /* PHY */
  61 #define CONFIG_PHY_MICREL
  62 #define CONFIG_PHY_MICREL_KSZ9021
  63 #define CONFIG_KSZ9021_CLK_SKEW_ENV     "micrel-ksz9021-clk-skew"
  64 #define CONFIG_KSZ9021_CLK_SKEW_VAL     0xf0f0
  65 #define CONFIG_KSZ9021_DATA_SKEW_ENV    "micrel-ksz9021-data-skew"
  66 #define CONFIG_KSZ9021_DATA_SKEW_VAL    0x0
  67
  68 #endif
  69
  70 /* USB */
  71 #ifdef CONFIG_CMD_USB
  72 #define CONFIG_USB_DWC2_REG_ADDR        SOCFPGA_USB1_ADDRESS
  73 #endif
  74 #define CONFIG_G_DNL_MANUFACTURER      "Altera"
  75
  76 /* Extra Environment */
  77 #define CONFIG_HOSTNAME         socfpga_cyclone5
  78
  79 #define CONFIG_EXTRA_ENV_SETTINGS \
  80         "verify=n\0" \
  81         "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  82         "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
  83                 "bootm ${loadaddr} - ${fdt_addr}\0" \
  84         "bootimage=zImage\0" \
  85         "fdt_addr=100\0" \
  86         "fdtimage=socfpga.dtb\0" \
  87                 "fsloadcmd=ext2load\0" \
  88         "bootm ${loadaddr} - ${fdt_addr}\0" \
  89         "mmcroot=/dev/mmcblk0p2\0" \
  90         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  91                 " root=${mmcroot} rw rootwait;" \
  92                 "bootz ${loadaddr} - ${fdt_addr}\0" \
  93         "mmcload=mmc rescan;" \
  94                 "load mmc 0:1 ${loadaddr} ${bootimage};" \
  95                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  96         "qspiroot=/dev/mtdblock0\0" \
  97         "qspirootfstype=jffs2\0" \
  98         "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
  99                 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 100                 "bootm ${loadaddr} - ${fdt_addr}\0"
 101
 102 /* The rest of the configuration is shared */
 103 #include <configs/socfpga_common.h>
 104
 105 #endif  /* __CONFIG_SOCFPGA_CYCLONE5_H__ */