include/configs/socfpga_sr1500.h

   1 /*
   2  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_SR1500_H__
   7 #define __CONFIG_SOCFPGA_SR1500_H__
   8
   9 #include <asm/arch/base_addr_ac5.h>
  10
  11 #define CONFIG_BOARD_EARLY_INIT_F
  12
  13 #define CONFIG_SYS_NO_FLASH
  14 #define CONFIG_DOS_PARTITION
  15 #define CONFIG_FAT_WRITE
  16
  17 #define CONFIG_HW_WATCHDOG
  18
  19 /* Memory configurations */
  20 #define PHYS_SDRAM_1_SIZE               0x40000000      /* 1GiB on SR1500 */
  21
  22 /* Booting Linux */
  23 #define CONFIG_BOOTFILE         "uImage"
  24 #define CONFIG_BOOTARGS         "console=ttyS0," __stringify(CONFIG_BAUDRATE)
  25 #define CONFIG_BOOTCOMMAND      "run mmcload; run mmcboot"
  26 #define CONFIG_LOADADDR         0x01000000
  27 #define CONFIG_SYS_LOAD_ADDR    CONFIG_LOADADDR
  28
  29 /* Ethernet on SoC (EMAC) */
  30 #define CONFIG_PHY_INTERFACE_MODE       PHY_INTERFACE_MODE_RGMII
  31 /* The PHY is autodetected, so no MII PHY address is needed here */
  32 #define CONFIG_PHY_MARVELL
  33 #define PHY_ANEG_TIMEOUT        8000
  34
  35 #define CONFIG_EXTRA_ENV_SETTINGS \
  36         "verify=n\0" \
  37         "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  38         "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
  39                 "bootm ${loadaddr} - ${fdt_addr}\0" \
  40         "bootimage=zImage\0" \
  41         "fdt_addr=100\0" \
  42         "fdtimage=socfpga.dtb\0" \
  43                 "fsloadcmd=ext2load\0" \
  44         "bootm ${loadaddr} - ${fdt_addr}\0" \
  45         "mmcroot=/dev/mmcblk0p2\0" \
  46         "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  47                 " root=${mmcroot} rw rootwait;" \
  48                 "bootz ${loadaddr} - ${fdt_addr}\0" \
  49         "mmcload=mmc rescan;" \
  50                 "load mmc 0:1 ${loadaddr} ${bootimage};" \
  51                 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  52         "qspiload=sf probe && mtdparts default && run ubiload\0" \
  53         "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
  54                 " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
  55                 "bootz ${loadaddr} - ${fdt_addr}\0" \
  56         "ubiload=ubi part UBI && ubifsmount ubi0 && " \
  57                 "ubifsload ${loadaddr} /boot/${bootimage} && " \
  58                 "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
  59
  60 /* Environment */
  61 #define CONFIG_ENV_IS_IN_SPI_FLASH
  62
  63 /* Enable SPI NOR flash reset, needed for SPI booting */
  64 #define CONFIG_SPI_N25Q256A_RESET
  65
  66 /*
  67  * Bootcounter
  68  */
  69 #define CONFIG_BOOTCOUNT_LIMIT
  70 /* last 2 lwords in OCRAM */
  71 #define CONFIG_SYS_BOOTCOUNT_ADDR       0xfffffff8
  72 #define CONFIG_SYS_BOOTCOUNT_BE
  73
  74 /* Environment setting for SPI flash */
  75 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  76 #define CONFIG_ENV_SECT_SIZE    (64 * 1024)
  77 #define CONFIG_ENV_SIZE         (16 * 1024)
  78 #define CONFIG_ENV_OFFSET       0x000e0000
  79 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
  80 #define CONFIG_ENV_SPI_BUS      0
  81 #define CONFIG_ENV_SPI_CS       0
  82 #define CONFIG_ENV_SPI_MODE     SPI_MODE_3
  83 #define CONFIG_ENV_SPI_MAX_HZ   100000000       /* Use max of 100MHz */
  84 #define CONFIG_SF_DEFAULT_SPEED 100000000
  85
  86 /*
  87  * The QSPI NOR flash layout on SR1500:
  88  *
  89  * 0000.0000 - 0003.ffff: SPL (4 times)
  90  * 0004.0000 - 000d.ffff: U-Boot
  91  * 000e.0000 - 000e.ffff: env1
  92  * 000f.0000 - 000f.ffff: env2
  93  */
  94
  95 /* The rest of the configuration is shared */
  96 #include <configs/socfpga_common.h>
  97
  98 #endif  /* __CONFIG_SOCFPGA_SR1500_H__ */