include/configs/stxgp3.h

   1 /*
   2  * (C) Copyright 2003 Embedded Edge, LLC
   3  * Dan Malek <dan@embeddededge.com>
   4  * Copied from ADS85xx.
   5  * Updates for Silicon Tx GP3 8560 board.
   6  *
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /* mpc8560ads board configuration file */
  30 /* please refer to doc/README.mpc85xx for more info */
  31 /* make sure you change the MAC address and other network params first,
  32  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /* High Level Configuration Options */
  39 #define CONFIG_BOOKE            1       /* BOOKE                */
  40 #define CONFIG_E500             1       /* BOOKE e500 family    */
  41 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560      */
  42 #define CONFIG_CPM2             1       /* has CPM2 */
  43 #define CONFIG_STXGP3           1       /* Silicon Tx GPPP board specific*/
  44
  45 #undef  CONFIG_PCI                      /* pci ethernet support */
  46 #define CONFIG_TSEC_ENET                /* tsec ethernet support*/
  47 #undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
  48 #define CONFIG_ENV_OVERWRITE
  49 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  50 #undef  CONFIG_DDR_ECC                  /* only for ECC DDR module */
  51 #define CONFIG_DDR_DLL                  /* possible DLL fix needed */
  52 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
  53
  54 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  55
  56 /* sysclk for MPC85xx
  57  */
  58
  59 #define CONFIG_SYS_CLK_FREQ     33333333 /* most pci cards are 33Mhz */
  60
  61 /* Blinkin' LEDs for Robert :-)
  62 */
  63 #define CONFIG_SHOW_ACTIVITY 1
  64
  65 /*
  66  * These can be toggled for performance analysis, otherwise use default.
  67  */
  68 #define CONFIG_L2_CACHE                     /* toggle L2 cache         */
  69 #define  CONFIG_BTB                          /* toggle branch predition */
  70 #define  CONFIG_ADDR_STREAMING               /* toggle addr streaming   */
  71
  72 #define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
  73
  74 #undef  CFG_DRAM_TEST                       /* memory test, takes time  */
  75 #define CFG_MEMTEST_START       0x00200000  /* memtest region */
  76 #define CFG_MEMTEST_END         0x00400000
  77
  78
  79 /* Localbus SDRAM is an option, not all boards have it.
  80  * This address, however, is used to configure a 256M local bus
  81  * window that includes the Config latch below.
  82  */
  83 #define CFG_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
  84 #define CFG_LBC_SDRAM_SIZE      256             /* LBC SDRAM is 64MB    */
  85
  86 #define CFG_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
  87 #define CFG_BR0_PRELIM        0xff001801      /* port size 32bit      */
  88
  89 #define CFG_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
  90 #define CFG_MAX_FLASH_BANKS     1               /* number of banks      */
  91 #define CFG_MAX_FLASH_SECT      136             /* sectors per device   */
  92 #undef  CFG_FLASH_CHECKSUM
  93 #define CFG_FLASH_ERASE_TOUT    60000   /* Timeout for Flash Erase (in ms)      */
  94 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
  95
  96 /* The configuration latch is Chip Select 1.
  97  * It's an 8-bit latch in the lower 8 bits of the word.
  98  */
  99 #define CFG_BR1_PRELIM          0xfc001801      /* 32-bit port */
 100 #define CFG_OR1_PRELIM          0xffff0ff7      /* 64K is enough */
 101 #define CFG_LBC_LCLDEVS_BASE    0xfc000000      /* Base of localbus devices */
 102
 103 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor     */
 104
 105 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 106 #define CFG_RAMBOOT
 107 #else
 108 #undef  CFG_RAMBOOT
 109 #endif
 110
 111 #ifdef CFG_RAMBOOT
 112 #define CFG_CCSRBAR_DEFAULT     0x40000000      /* CCSRBAR by BDI cfg   */
 113 #else
 114 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default      */
 115 #endif
 116 #define CFG_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
 117 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
 118
 119
 120 /*
 121  * DDR Setup
 122  */
 123
 124 /*
 125  * Base addresses -- Note these are effective addresses where the
 126  * actual resources get mapped (not physical addresses)
 127  */
 128 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory  */
 129 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 130
 131 #define SPD_EEPROM_ADDRESS      0x54            /*  DDR DIMM */
 132
 133 #undef CONFIG_CLOCKS_IN_MHZ
 134
 135 /* local bus definitions */
 136 #define CFG_BR2_PRELIM          0xf8001861      /* 64MB localbus SDRAM  */
 137 #define CFG_OR2_PRELIM          0xfc006901
 138 #define CFG_LBC_LCRR            0x00030004      /* local bus freq       */
 139 #define CFG_LBC_LBCR            0x00000000
 140 #define CFG_LBC_LSRT            0x20000000
 141 #define CFG_LBC_MRTPR           0x20000000
 142 #define CFG_LBC_LSDMR_1         0x2861b723
 143 #define CFG_LBC_LSDMR_2         0x0861b723
 144 #define CFG_LBC_LSDMR_3         0x0861b723
 145 #define CFG_LBC_LSDMR_4         0x1861b723
 146 #define CFG_LBC_LSDMR_5         0x4061b723
 147
 148 #define CONFIG_L1_INIT_RAM
 149 #define CFG_INIT_RAM_LOCK       1
 150 #define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
 151 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 152
 153 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 154 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 155 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 156
 157 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 158 #define CFG_MALLOC_LEN          (128 * 1024)    /* Reserved for malloc */
 159
 160 /* Serial Port */
 161 #define CONFIG_CONS_ON_SCC                      /* define if console on SCC */
 162 #undef  CONFIG_CONS_NONE                        /* define if console on something else */
 163 #define CONFIG_CONS_INDEX       2               /* which serial channel for console */
 164
 165 #define CONFIG_BAUDRATE         38400
 166
 167 #define CFG_BAUDRATE_TABLE  \
 168         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 169
 170 /* Use the HUSH parser */
 171 #define CFG_HUSH_PARSER
 172 #ifdef  CFG_HUSH_PARSER
 173 #define CFG_PROMPT_HUSH_PS2 "> "
 174 #endif
 175
 176 /*
 177  * I2C
 178  */
 179 #define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 180 #define CONFIG_HARD_I2C         /* I2C with hardware support*/
 181 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 182 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 183 #define CFG_I2C_SLAVE           0x7F
 184 #if 0
 185 #define CFG_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
 186 #else
 187 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
 188 #undef CFG_I2C_NOPROBES
 189 #endif
 190 #define CFG_I2C_OFFSET          0x3000
 191
 192 /* RapdIO Map configuration, mapped 1:1.
 193 */
 194 #define CFG_RIO_MEM_BASE        0xc0000000
 195 #define CFG_RIO_MEM_PHYS        CFG_RIO_MEM_BASE
 196 #define CFG_RIO_MEM_SIZE        0x200000000     /* 512 M */
 197
 198 /* Standard 8560 PCI addressing, mapped 1:1.
 199 */
 200 #define CFG_PCI1_MEM_BASE       0x80000000
 201 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 202 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 203 #define CFG_PCI1_IO_BASE        0xe2000000
 204 #define CFG_PCI1_IO_PHYS        CFG_PCI1_IO_BASE
 205 #define CFG_PCI1_IO_SIZE        0x01000000      /* 16 M */
 206
 207 #if defined(CONFIG_PCI)                 /* PCI Ethernet card */
 208
 209 #define CONFIG_NET_MULTI
 210 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 211
 212 #undef CONFIG_EEPRO100
 213 #undef CONFIG_TULIP
 214
 215 #if !defined(CONFIG_PCI_PNP)
 216   #define PCI_ENET0_IOADDR      0xe0000000
 217   #define PCI_ENET0_MEMADDR     0xe0000000
 218   #define PCI_IDSEL_NUMBER      0x0c    /* slot0->3(IDSEL)=12->15 */
 219 #endif
 220
 221 #undef CONFIG_PCI_SCAN_SHOW
 222 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 223
 224 #endif /* CONFIG_PCI */
 225
 226 #if defined(CONFIG_TSEC_ENET)
 227
 228 #ifndef CONFIG_NET_MULTI
 229 #define CONFIG_NET_MULTI        1
 230 #endif
 231
 232 #define CONFIG_MII              1       /* MII PHY management           */
 233
 234 #define CONFIG_TSEC1    1
 235 #define CONFIG_TSEC1_NAME       "TSEC0"
 236 #define CONFIG_TSEC2    1
 237 #define CONFIG_TSEC2_NAME       "TSEC1"
 238
 239 #define TSEC1_PHY_ADDR          2
 240 #define TSEC2_PHY_ADDR          4
 241 #define TSEC1_PHYIDX            0
 242 #define TSEC2_PHYIDX            0
 243 #define TSEC1_FLAGS             TSEC_GIGABIT
 244 #define TSEC2_FLAGS             TSEC_GIGABIT
 245 #define CONFIG_ETHPRIME         "TSEC0"
 246
 247 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 248
 249 #define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
 250 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 251 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
 252
 253 #if (CONFIG_ETHER_INDEX == 2)
 254   /*
 255    * - Rx-CLK is CLK13
 256    * - Tx-CLK is CLK14
 257    * - Select bus for bd/buffers
 258    * - Full duplex
 259    */
 260   #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 261   #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 262   #define CFG_CPMFCR_RAMTYPE    0
 263 #if 0
 264   #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
 265 #else
 266   #define CFG_FCC_PSMR          0
 267 #endif
 268   #define FETH2_RST             0x01
 269 #elif (CONFIG_ETHER_INDEX == 3)
 270   /* need more definitions here for FE3 */
 271   #define FETH3_RST             0x80
 272 #endif                                  /* CONFIG_ETHER_INDEX */
 273
 274 /* MDIO is done through the TSEC0 control.
 275 */
 276 #define CONFIG_MII                      /* MII PHY management */
 277 #undef CONFIG_BITBANGMII                /* bit-bang MII PHY management  */
 278
 279 #endif
 280
 281 /* Environment */
 282 /* We use the top boot sector flash, so we have some 16K sectors for env
 283  */
 284 #ifndef CFG_RAMBOOT
 285   #define CFG_ENV_IS_IN_FLASH   1
 286   #define CFG_ENV_ADDR          (CFG_MONITOR_BASE + 0x60000)
 287   #define CFG_ENV_SECT_SIZE     0x4000  /* 16K (one top sector) for env */
 288   #define CFG_ENV_SIZE          0x2000
 289 #else
 290   #define CFG_NO_FLASH          1       /* Flash is not usable now      */
 291   #define CFG_ENV_IS_NOWHERE    1       /* Store ENV in memory only     */
 292   #define CFG_ENV_ADDR          (CFG_MONITOR_BASE - 0x1000)
 293   #define CFG_ENV_SIZE          0x2000
 294 #endif
 295
 296 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
 297 #define CONFIG_BOOTCOMMAND      "bootm 0xff000000 0xff100000"
 298 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 299
 300 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 301 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 302
 303 /*
 304  * BOOTP options
 305  */
 306 #define CONFIG_BOOTP_BOOTFILESIZE
 307 #define CONFIG_BOOTP_BOOTPATH
 308 #define CONFIG_BOOTP_GATEWAY
 309 #define CONFIG_BOOTP_HOSTNAME
 310
 311
 312 /*
 313  * Command line configuration.
 314  */
 315 #include <config_cmd_default.h>
 316
 317 #define CONFIG_CMD_PING
 318 #define CONFIG_CMD_I2C
 319
 320 #if defined(CFG_RAMBOOT)
 321     #undef CONFIG_CMD_ENV
 322     #undef CONFIG_CMD_LOADS
 323 #else
 324     #define CONFIG_CMD_ELF
 325 #endif
 326
 327 #if defined(CONFIG_PCI)
 328     #define CONFIG_CMD_PCI
 329 #endif
 330
 331 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 332     #define CONFIG_CMD_MII
 333 #endif
 334
 335
 336 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 337
 338 /*
 339  * Miscellaneous configurable options
 340  */
 341 #define CFG_LONGHELP                    /* undef to save memory         */
 342 #define CFG_PROMPT      "GPPP=> "       /* Monitor Command Prompt       */
 343 #if defined(CONFIG_CMD_KGDB)
 344 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 345 #else
 346 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 347 #endif
 348 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 349 #define CFG_MAXARGS     16              /* max number of command args   */
 350 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 351 #define CFG_LOAD_ADDR   0x1000000       /* default load address */
 352 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 353
 354 /*
 355  * For booting Linux, the board info and command line data
 356  * have to be in the first 8 MB of memory, since this is
 357  * the maximum mapped by the Linux kernel during initialization.
 358  */
 359 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 360
 361 /*
 362  * Internal Definitions
 363  *
 364  * Boot Flags
 365  */
 366 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 367 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 368
 369 #if defined(CONFIG_CMD_KGDB)
 370 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 371 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 372 #endif
 373
 374 /*Note: change below for your network setting!!! */
 375 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 376 #define CONFIG_HAS_ETH0
 377 #define CONFIG_ETHADDR   00:e0:0c:07:9b:8a
 378 #define CONFIG_HAS_ETH1
 379 #define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
 380 #define CONFIG_HAS_ETH2
 381 #define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
 382 #endif
 383
 384 #define CONFIG_SERVERIP         192.168.85.1
 385 #define CONFIG_IPADDR           192.168.85.60
 386 #define CONFIG_GATEWAYIP        192.168.85.1
 387 #define CONFIG_NETMASK          255.255.255.0
 388 #define CONFIG_HOSTNAME         STX_GP3
 389 #define CONFIG_ROOTPATH         /gppproot
 390 #define CONFIG_BOOTFILE         uImage
 391 #define CONFIG_LOADADDR         0x1000000
 392
 393 #endif  /* __CONFIG_H */