include/configs/stxssa.h

   1 /*
   2  * (C) Copyright 2005 Embedded Alley Solutions, Inc.
   3  * Dan Malek <dan@embeddedalley.com>
   4  * Copied from STx GP3.
   5  * Updates for Silicon Tx GP3 SSA board.
   6  *
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /* mpc8560ads board configuration file */
  30 /* please refer to doc/README.mpc85xx for more info */
  31 /* make sure you change the MAC address and other network params first,
  32  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /* High Level Configuration Options */
  39 #define CONFIG_BOOKE            1       /* BOOKE                */
  40 #define CONFIG_E500             1       /* BOOKE e500 family    */
  41 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560      */
  42 #define CONFIG_CPM2             1       /* has CPM2 */
  43 #define CONFIG_STXSSA           1       /* Silicon Tx GPPP SSA board specific*/
  44 #define CONFIG_MPC8560          1
  45
  46 #define CONFIG_PCI                      /* PCI ethernet support */
  47 #define CONFIG_TSEC_ENET                /* tsec ethernet support*/
  48 #undef CONFIG_ETHER_ON_FCC              /* cpm FCC ethernet support */
  49 #define CONFIG_ENV_OVERWRITE
  50
  51 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  52
  53 /* sysclk for MPC85xx
  54  */
  55
  56 #define CONFIG_SYS_CLK_FREQ     33000000 /* most pci cards are 33Mhz */
  57
  58 /* Blinkin' LEDs for Robert :-)
  59 */
  60 #define CONFIG_SHOW_ACTIVITY 1
  61
  62 /*
  63  * These can be toggled for performance analysis, otherwise use default.
  64  */
  65 #define CONFIG_L2_CACHE                         /* toggle L2 cache             */
  66 #define  CONFIG_BTB                             /* toggle branch predition */
  67 #define  CONFIG_ADDR_STREAMING                  /* toggle addr streaming        */
  68
  69 #define CONFIG_BOARD_EARLY_INIT_F   1           /* Call board_pre_init   */
  70
  71 #undef  CFG_DRAM_TEST                           /* memory test, takes time      */
  72 #define CFG_MEMTEST_START       0x00200000      /* memtest region */
  73 #define CFG_MEMTEST_END         0x00400000
  74
  75
  76 /* Localbus connector.  There are many options that can be
  77  * connected here, including sdram or lots of flash.
  78  * This address, however, is used to configure a 256M local bus
  79  * window that includes the Config latch below.
  80  */
  81 #define CFG_LBC_OPTION_BASE     0xF0000000      /* Localbus Extension */
  82 #define CFG_LBC_OPTION_SIZE     256             /* 256MB */
  83
  84 /* There are various flash options used, we configure for the largest,
  85  * which is 64Mbytes.  The CFI works fine and will discover the proper
  86  * sizes.
  87  */
  88 #ifdef CONFIG_STXSSA_4M
  89 #define CFG_FLASH_BASE          0xFFC00000      /* start of  4 MiB flash */
  90 #else
  91 #define CFG_FLASH_BASE          0xFC000000      /* start of 64 MiB flash */
  92 #endif
  93 #define CFG_BR0_PRELIM  (CFG_FLASH_BASE | 0x1801) /* port size 32bit     */
  94 #define CFG_OR0_PRELIM  (CFG_FLASH_BASE | 0x0FF7)
  95
  96 #define CFG_FLASH_CFI           1
  97 #define CONFIG_FLASH_CFI_DRIVER 1
  98 #undef CFG_FLASH_USE_BUFFER_WRITE       /* use buffered writes (20x faster) */
  99 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip */
 100 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks   */
 101
 102 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
 103
 104 #define CFG_FLASH_PROTECTION
 105
 106 /* The configuration latch is Chip Select 1.
 107  * It's an 8-bit latch in the lower 8 bits of the word.
 108  */
 109 #define CFG_LBC_CFGLATCH_BASE   0xFB000000      /* Base of config latch */
 110 #define CFG_BR1_PRELIM          0xFB001801      /* 32-bit port */
 111 #define CFG_OR1_PRELIM          0xFFFF0FF7      /* 64K is enough */
 112
 113 #define CFG_MONITOR_BASE        TEXT_BASE       /* start of monitor     */
 114
 115 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 116 #define CFG_RAMBOOT
 117 #else
 118 #undef  CFG_RAMBOOT
 119 #endif
 120
 121 #ifdef CFG_RAMBOOT
 122 #define CFG_CCSRBAR_DEFAULT     0x40000000      /* CCSRBAR by BDI cfg   */
 123 #else
 124 #define CFG_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default      */
 125 #endif
 126 #define CFG_CCSRBAR             0xe0000000      /* relocated CCSRBAR    */
 127 #define CFG_CCSRBAR_PHYS        CFG_CCSRBAR     /* physical addr of CCSRBAR */
 128 #define CFG_IMMR                CFG_CCSRBAR     /* PQII uses CFG_IMMR   */
 129
 130 /* DDR Setup */
 131 #define CONFIG_FSL_DDR1
 132 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 133 #define CONFIG_DDR_SPD
 134 #undef CONFIG_FSL_DDR_INTERACTIVE
 135
 136 #undef  CONFIG_DDR_ECC                  /* only for ECC DDR module */
 137 #undef CONFIG_DDR_DLL                   /* possible DLL fix needed */
 138 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
 139
 140 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 141
 142 #define CFG_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
 143 #define CFG_SDRAM_BASE          CFG_DDR_SDRAM_BASE
 144
 145 #define CONFIG_NUM_DDR_CONTROLLERS      1
 146 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 147 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 148
 149 /* I2C addresses of SPD EEPROMs */
 150 #define SPD_EEPROM_ADDRESS      0x54    /* CTLR 0 DIMM 0 */
 151
 152 #undef CONFIG_CLOCKS_IN_MHZ
 153
 154 /* local bus definitions */
 155 #define CFG_BR2_PRELIM          0xf8001861      /* 64MB localbus SDRAM  */
 156 #define CFG_OR2_PRELIM          0xfc006901
 157 #define CFG_LBC_LCRR            0x00030004      /* local bus freq       */
 158 #define CFG_LBC_LBCR            0x00000000
 159 #define CFG_LBC_LSRT            0x20000000
 160 #define CFG_LBC_MRTPR           0x20000000
 161 #define CFG_LBC_LSDMR_1         0x2861b723
 162 #define CFG_LBC_LSDMR_2         0x0861b723
 163 #define CFG_LBC_LSDMR_3         0x0861b723
 164 #define CFG_LBC_LSDMR_4         0x1861b723
 165 #define CFG_LBC_LSDMR_5         0x4061b723
 166
 167 #define CONFIG_L1_INIT_RAM
 168 #define CFG_INIT_RAM_LOCK       1
 169 #define CFG_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
 170 #define CFG_INIT_RAM_END        0x4000          /* End of used area in RAM */
 171
 172 #define CFG_GBL_DATA_SIZE       128             /* num bytes initial data */
 173 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 174 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 175
 176 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Mon */
 177 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserved for malloc */
 178
 179 /* Serial Port */
 180 #define CONFIG_CONS_INDEX     2
 181 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 182 #define CFG_NS16550
 183 #define CFG_NS16550_SERIAL
 184 #define CFG_NS16550_REG_SIZE    1
 185 #define CFG_NS16550_CLK         get_bus_freq(0)
 186
 187 #define CFG_BAUDRATE_TABLE  \
 188         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 189
 190 #define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
 191 #define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)
 192
 193 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 194 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 195 #ifdef  CFG_HUSH_PARSER
 196 #define CFG_PROMPT_HUSH_PS2 "> "
 197 #endif
 198
 199 /*
 200  * I2C
 201  */
 202 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver */
 203 #define  CONFIG_HARD_I2C                /* I2C with hardware support*/
 204 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 205 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 206 #define CFG_I2C_SLAVE           0x7F
 207 #undef CFG_I2C_NOPROBES
 208 #define CFG_I2C_OFFSET          0x3000
 209
 210 /* I2C RTC */
 211 #define CONFIG_RTC_DS1337               /* This is really a DS1339 RTC  */
 212 #define CFG_I2C_RTC_ADDR        0x68    /* at address 0x68              */
 213
 214 /* I2C EEPROM.  AT24C32, we keep our environment in here.
 215 */
 216 #define CFG_I2C_EEPROM_ADDR             0x51    /* 1010001x             */
 217 #define CFG_I2C_EEPROM_ADDR_LEN         2
 218 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write  */
 219 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 220 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 221
 222 /*
 223  * Standard 8555 PCI mapping.
 224  * Addresses are mapped 1-1.
 225  */
 226 #define CFG_PCI1_MEM_BASE       0x80000000
 227 #define CFG_PCI1_MEM_PHYS       CFG_PCI1_MEM_BASE
 228 #define CFG_PCI1_MEM_SIZE       0x20000000      /* 512M */
 229 #define CFG_PCI1_IO_BASE        0x00000000
 230 #define CFG_PCI1_IO_PHYS        0xe2000000
 231 #define CFG_PCI1_IO_SIZE        0x01000000      /* 16M */
 232
 233 #define CFG_PCI2_MEM_BASE       0xa0000000
 234 #define CFG_PCI2_MEM_PHYS       CFG_PCI2_MEM_BASE
 235 #define CFG_PCI2_MEM_SIZE       0x20000000      /* 512M */
 236 #define CFG_PCI2_IO_BASE        0x00000000
 237 #define CFG_PCI2_IO_PHYS        0xe3000000
 238 #define CFG_PCI2_IO_SIZE        0x01000000      /* 16M */
 239
 240 #if defined(CONFIG_PCI)                 /* PCI Ethernet card */
 241 #define CONFIG_MPC85XX_PCI2     1
 242 #define CONFIG_NET_MULTI
 243 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 244
 245 #define CONFIG_EEPRO100
 246 #define CONFIG_TULIP
 247
 248 #if !defined(CONFIG_PCI_PNP)
 249   #define PCI_ENET0_IOADDR      0xe0000000
 250   #define PCI_ENET0_MEMADDR     0xe0000000
 251   #define PCI_IDSEL_NUMBER      0x0c    /* slot0->3(IDSEL)=12->15 */
 252 #endif
 253
 254 #define CONFIG_PCI_SCAN_SHOW
 255 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 256
 257 #endif /* CONFIG_PCI */
 258
 259 #if defined(CONFIG_TSEC_ENET)
 260
 261 #ifndef CONFIG_NET_MULTI
 262 #define CONFIG_NET_MULTI        1
 263 #endif
 264
 265 #define CONFIG_MII              1       /* MII PHY management           */
 266
 267 #define CONFIG_TSEC1    1
 268 #define CONFIG_TSEC1_NAME       "TSEC0"
 269 #define CONFIG_TSEC2    1
 270 #define CONFIG_TSEC2_NAME       "TSEC1"
 271
 272 #define TSEC1_PHY_ADDR          2
 273 #define TSEC2_PHY_ADDR          4
 274 #define TSEC1_PHYIDX            0
 275 #define TSEC2_PHYIDX            0
 276 #define TSEC1_FLAGS             TSEC_GIGABIT
 277 #define TSEC2_FLAGS             TSEC_GIGABIT
 278 #define CONFIG_ETHPRIME         "TSEC0"
 279
 280 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 281
 282 #define CONFIG_ETHER_ON_FCC2            /* define if ether on FCC   */
 283 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 284 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
 285
 286 #if (CONFIG_ETHER_INDEX == 2)
 287   /*
 288    * - Rx-CLK is CLK13
 289    * - Tx-CLK is CLK14
 290    * - Select bus for bd/buffers
 291    * - Full duplex
 292    */
 293   #define CFG_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 294   #define CFG_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 295   #define CFG_CPMFCR_RAMTYPE    0
 296 #if 0
 297   #define CFG_FCC_PSMR          (FCC_PSMR_FDE)
 298 #else
 299   #define CFG_FCC_PSMR          0
 300 #endif
 301   #define FETH2_RST             0x01
 302 #elif (CONFIG_ETHER_INDEX == 3)
 303   /* need more definitions here for FE3 */
 304   #define FETH3_RST             0x80
 305 #endif                                  /* CONFIG_ETHER_INDEX */
 306
 307 /* MDIO is done through the TSEC0 control.
 308 */
 309 #define CONFIG_MII                      /* MII PHY management */
 310 #undef CONFIG_BITBANGMII                /* bit-bang MII PHY management  */
 311
 312 #endif
 313
 314 /* Environment - default config is in flash, see below */
 315 #if 0   /* in EEPROM */
 316 # define CONFIG_ENV_IS_IN_EEPROM        1
 317 # define CONFIG_ENV_OFFSET              0
 318 # define CONFIG_ENV_SIZE                2048
 319 #else   /* in flash */
 320 # define CONFIG_ENV_IS_IN_FLASH 1
 321 # ifdef CONFIG_STXSSA_4M
 322 #  define CONFIG_ENV_SECT_SIZE  0x20000
 323 # else  /* default configuration - 64 MiB flash */
 324 #  define CONFIG_ENV_SECT_SIZE  0x40000
 325 # endif
 326 # define CONFIG_ENV_ADDR                (CFG_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 327 # define CONFIG_ENV_SIZE                0x4000
 328 # define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 329 # define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
 330 #endif
 331
 332 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 333 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 334
 335 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
 336
 337
 338 /*
 339  * BOOTP options
 340  */
 341 #define CONFIG_BOOTP_BOOTFILESIZE
 342 #define CONFIG_BOOTP_BOOTPATH
 343 #define CONFIG_BOOTP_GATEWAY
 344 #define CONFIG_BOOTP_HOSTNAME
 345
 346
 347 /*
 348  * Command line configuration.
 349  */
 350 #include <config_cmd_default.h>
 351
 352 #define CONFIG_CMD_DATE
 353 #define CONFIG_CMD_DHCP
 354 #define CONFIG_CMD_EEPROM
 355 #define CONFIG_CMD_I2C
 356 #define CONFIG_CMD_NFS
 357 #define CONFIG_CMD_PING
 358 #define CONFIG_CMD_SNTP
 359
 360 #if defined(CONFIG_PCI)
 361     #define CONFIG_CMD_PCI
 362 #endif
 363
 364 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 365     #define CONFIG_CMD_MII
 366 #endif
 367
 368 #if defined(CFG_RAMBOOT)
 369     #undef CONFIG_CMD_ENV
 370     #undef CONFIG_CMD_LOADS
 371 #else
 372     #define CONFIG_CMD_ELF
 373 #endif
 374
 375
 376 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 377
 378 /*
 379  * Miscellaneous configurable options
 380  */
 381 #define CFG_LONGHELP                    /* undef to save memory         */
 382 #define CFG_PROMPT      "SSA=> "        /* Monitor Command Prompt       */
 383 #if defined(CONFIG_CMD_KGDB)
 384 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 385 #else
 386 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 387 #endif
 388 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 389 #define CFG_MAXARGS     16              /* max number of command args   */
 390 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 391 #define CFG_LOAD_ADDR   0x1000000       /* default load address */
 392 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 393
 394 /*
 395  * For booting Linux, the board info and command line data
 396  * have to be in the first 8 MB of memory, since this is
 397  * the maximum mapped by the Linux kernel during initialization.
 398  */
 399 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 400
 401 /*
 402  * Internal Definitions
 403  *
 404  * Boot Flags
 405  */
 406 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 407 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 408
 409 #if defined(CONFIG_CMD_KGDB)
 410 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 411 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 412 #endif
 413
 414 /*Note: change below for your network setting!!! */
 415 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 416 #define CONFIG_HAS_ETH0
 417 #define CONFIG_ETHADDR   00:e0:0c:07:9b:8a
 418 #define CONFIG_HAS_ETH1
 419 #define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
 420 #define CONFIG_HAS_ETH2
 421 #define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
 422 #endif
 423
 424 /*
 425  * Environment in EEPROM is compatible with different flash sector sizes,
 426  * but only little space is available, so we use a very simple setup.
 427  * With environment in flash, we use a more powerful default configuration.
 428  */
 429 #ifdef CONFIG_ENV_IS_IN_EEPROM          /* use restricted "standard" environment */
 430
 431 #define CONFIG_BAUDRATE         38400
 432
 433 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 434 #define CONFIG_BOOTCOMMAND      "bootm 0xffc00000 0xffd00000"
 435 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
 436 #define CONFIG_SERVERIP         192.168.85.1
 437 #define CONFIG_IPADDR           192.168.85.60
 438 #define CONFIG_GATEWAYIP        192.168.85.1
 439 #define CONFIG_NETMASK          255.255.255.0
 440 #define CONFIG_HOSTNAME         STX_SSA
 441 #define CONFIG_ROOTPATH         /gppproot
 442 #define CONFIG_BOOTFILE         uImage
 443 #define CONFIG_LOADADDR         0x1000000
 444
 445 #else /* ENV IS IN FLASH                -- use a full-blown envionment */
 446
 447 #define CONFIG_BAUDRATE         115200
 448
 449 #define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 450
 451 #define CONFIG_PREBOOT  "echo;" \
 452         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 453         "echo"
 454
 455 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 456
 457 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 458         "hostname=gp3ssa\0"                                             \
 459         "bootfile=/tftpboot/gp3ssa/uImage\0"                            \
 460         "loadaddr=400000\0"                                             \
 461         "netdev=eth0\0"                                                 \
 462         "consdev=ttyS1\0"                                               \
 463         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 464                 "nfsroot=$serverip:$rootpath\0"                         \
 465         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 466         "addip=setenv bootargs $bootargs "                              \
 467                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 468                 ":$hostname:$netdev:off panic=1\0"                      \
 469         "addcons=setenv bootargs $bootargs "                            \
 470                 "console=$consdev,$baudrate\0"                          \
 471         "flash_nfs=run nfsargs addip addcons;"                          \
 472                 "bootm $kernel_addr\0"                                  \
 473         "flash_self=run ramargs addip addcons;"                         \
 474                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 475         "net_nfs=tftp $loadaddr $bootfile;"                             \
 476                 "run nfsargs addip addcons;bootm\0"                     \
 477         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 478         "kernel_addr=FC000000\0"                                        \
 479         "ramdisk_addr=FC200000\0"                                       \
 480         ""
 481 #define CONFIG_BOOTCOMMAND      "run flash_self"
 482
 483 #endif  /* CONFIG_ENV_IS_IN_EEPROM */
 484
 485 #endif  /* __CONFIG_H */