include/configs/stxssa.h

   1 /*
   2  * (C) Copyright 2005 Embedded Alley Solutions, Inc.
   3  * Dan Malek <dan@embeddedalley.com>
   4  * Copied from STx GP3.
   5  * Updates for Silicon Tx GP3 SSA board.
   6  *
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 /* mpc8560ads board configuration file */
  14 /* please refer to doc/README.mpc85xx for more info */
  15 /* make sure you change the MAC address and other network params first,
  16  * search for CONFIG_SERVERIP, etc. in this file
  17  */
  18
  19 #ifndef __CONFIG_H
  20 #define __CONFIG_H
  21
  22 /* High Level Configuration Options */
  23 #define CONFIG_BOOKE            1       /* BOOKE                */
  24 #define CONFIG_E500             1       /* BOOKE e500 family    */
  25 #define CONFIG_CPM2             1       /* has CPM2 */
  26 #define CONFIG_STXSSA           1       /* Silicon Tx GPPP SSA board specific*/
  27 #define CONFIG_MPC8560          1
  28
  29 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  30
  31 #define CONFIG_PCI                      /* PCI ethernet support */
  32 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  33 #define CONFIG_TSEC_ENET                /* tsec ethernet support*/
  34 #undef CONFIG_ETHER_ON_FCC              /* cpm FCC ethernet support */
  35 #define CONFIG_ENV_OVERWRITE
  36
  37 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  38
  39 /* sysclk for MPC85xx
  40  */
  41
  42 #define CONFIG_SYS_CLK_FREQ     33000000 /* most pci cards are 33Mhz */
  43
  44 /* Blinkin' LEDs for Robert :-)
  45 */
  46 #define CONFIG_SHOW_ACTIVITY 1
  47
  48 /*
  49  * These can be toggled for performance analysis, otherwise use default.
  50  */
  51 #define CONFIG_L2_CACHE                         /* toggle L2 cache             */
  52 #define  CONFIG_BTB                             /* toggle branch predition */
  53
  54 #define CONFIG_BOARD_EARLY_INIT_F   1           /* Call board_pre_init   */
  55
  56 #undef  CONFIG_SYS_DRAM_TEST                            /* memory test, takes time      */
  57 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  58 #define CONFIG_SYS_MEMTEST_END          0x00400000
  59
  60
  61 /* Localbus connector.  There are many options that can be
  62  * connected here, including sdram or lots of flash.
  63  * This address, however, is used to configure a 256M local bus
  64  * window that includes the Config latch below.
  65  */
  66 #define CONFIG_SYS_LBC_OPTION_BASE      0xF0000000      /* Localbus Extension */
  67 #define CONFIG_SYS_LBC_OPTION_SIZE      256             /* 256MB */
  68
  69 /* There are various flash options used, we configure for the largest,
  70  * which is 64Mbytes.  The CFI works fine and will discover the proper
  71  * sizes.
  72  */
  73 #ifdef CONFIG_STXSSA_4M
  74 #define CONFIG_SYS_FLASH_BASE           0xFFC00000      /* start of  4 MiB flash */
  75 #else
  76 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of 64 MiB flash */
  77 #endif
  78 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit      */
  79 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_FLASH_BASE | 0x0FF7)
  80
  81 #define CONFIG_SYS_FLASH_CFI            1
  82 #define CONFIG_FLASH_CFI_DRIVER 1
  83 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* use buffered writes (20x faster) */
  84 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
  85 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks   */
  86
  87 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  88
  89 #define CONFIG_SYS_FLASH_PROTECTION
  90
  91 /* The configuration latch is Chip Select 1.
  92  * It's an 8-bit latch in the lower 8 bits of the word.
  93  */
  94 #define CONFIG_SYS_LBC_CFGLATCH_BASE    0xFB000000      /* Base of config latch */
  95 #define CONFIG_SYS_BR1_PRELIM           0xFB001801      /* 32-bit port */
  96 #define CONFIG_SYS_OR1_PRELIM           0xFFFF0FF7      /* 64K is enough */
  97
  98 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
  99
 100 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 101 #define CONFIG_SYS_RAMBOOT
 102 #else
 103 #undef  CONFIG_SYS_RAMBOOT
 104 #endif
 105
 106 #ifdef CONFIG_SYS_RAMBOOT
 107 #define CONFIG_SYS_CCSRBAR_DEFAULT      0x40000000      /* CCSRBAR by BDI cfg   */
 108 #endif
 109
 110 #define CONFIG_SYS_CCSRBAR              0xe0000000
 111 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 112
 113 /* DDR Setup */
 114 #define CONFIG_SYS_FSL_DDR1
 115 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 116 #define CONFIG_DDR_SPD
 117 #undef CONFIG_FSL_DDR_INTERACTIVE
 118
 119 #undef  CONFIG_DDR_ECC                  /* only for ECC DDR module */
 120 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
 121
 122 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 123
 124 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 125 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 126
 127 #define CONFIG_NUM_DDR_CONTROLLERS      1
 128 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 129 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 130
 131 /* I2C addresses of SPD EEPROMs */
 132 #define SPD_EEPROM_ADDRESS      0x54    /* CTLR 0 DIMM 0 */
 133
 134 #undef CONFIG_CLOCKS_IN_MHZ
 135
 136 /* local bus definitions */
 137 #define CONFIG_SYS_BR2_PRELIM           0xf8001861      /* 64MB localbus SDRAM  */
 138 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 139 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* local bus freq       */
 140 #define CONFIG_SYS_LBC_LBCR             0x00000000
 141 #define CONFIG_SYS_LBC_LSRT             0x20000000
 142 #define CONFIG_SYS_LBC_MRTPR            0x20000000
 143 #define CONFIG_SYS_LBC_LSDMR_1          0x2861b723
 144 #define CONFIG_SYS_LBC_LSDMR_2          0x0861b723
 145 #define CONFIG_SYS_LBC_LSDMR_3          0x0861b723
 146 #define CONFIG_SYS_LBC_LSDMR_4          0x1861b723
 147 #define CONFIG_SYS_LBC_LSDMR_5          0x4061b723
 148
 149 #define CONFIG_SYS_INIT_RAM_LOCK        1
 150 #define CONFIG_SYS_INIT_RAM_ADDR        0x60000000      /* Initial RAM address  */
 151 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 152
 153 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 154 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 155
 156 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 157 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)    /* Reserved for malloc */
 158
 159 /* Serial Port */
 160 #define CONFIG_CONS_INDEX     2
 161 #define CONFIG_SYS_NS16550
 162 #define CONFIG_SYS_NS16550_SERIAL
 163 #define CONFIG_SYS_NS16550_REG_SIZE     1
 164 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 165
 166 #define CONFIG_SYS_BAUDRATE_TABLE  \
 167         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 168
 169 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 170 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 171
 172 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 173 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 174 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 175
 176 /* pass open firmware flat tree */
 177 #define CONFIG_OF_LIBFDT                1
 178 #define CONFIG_OF_BOARD_SETUP           1
 179 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 180
 181 /*
 182  * I2C
 183  */
 184 #define CONFIG_SYS_I2C
 185 #define CONFIG_SYS_I2C_FSL
 186 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 187 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 188 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 189 #undef CONFIG_SYS_I2C_NOPROBES
 190
 191 /* I2C RTC */
 192 #define CONFIG_RTC_DS1337               /* This is really a DS1339 RTC  */
 193 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 194
 195 /* I2C EEPROM.  AT24C32, we keep our environment in here.
 196 */
 197 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x51    /* 1010001x             */
 198 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 199 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write  */
 200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 201
 202 /*
 203  * Standard 8555 PCI mapping.
 204  * Addresses are mapped 1-1.
 205  */
 206 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 207 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 208 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 209 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 210 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 211 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M */
 212
 213 #define CONFIG_SYS_PCI2_MEM_BASE        0xa0000000
 214 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 215 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 216 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 217 #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
 218 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000      /* 16M */
 219
 220 #if defined(CONFIG_PCI)                 /* PCI Ethernet card */
 221 #define CONFIG_MPC85XX_PCI2     1
 222 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 223
 224 #define CONFIG_EEPRO100
 225 #define CONFIG_TULIP
 226
 227 #if !defined(CONFIG_PCI_PNP)
 228   #define PCI_ENET0_IOADDR      0xe0000000
 229   #define PCI_ENET0_MEMADDR     0xe0000000
 230   #define PCI_IDSEL_NUMBER      0x0c    /* slot0->3(IDSEL)=12->15 */
 231 #endif
 232
 233 #define CONFIG_PCI_SCAN_SHOW
 234 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 235
 236 #endif /* CONFIG_PCI */
 237
 238 #if defined(CONFIG_TSEC_ENET)
 239
 240 #define CONFIG_MII              1       /* MII PHY management           */
 241
 242 #define CONFIG_TSEC1    1
 243 #define CONFIG_TSEC1_NAME       "TSEC0"
 244 #define CONFIG_TSEC2    1
 245 #define CONFIG_TSEC2_NAME       "TSEC1"
 246
 247 #define TSEC1_PHY_ADDR          2
 248 #define TSEC2_PHY_ADDR          4
 249 #define TSEC1_PHYIDX            0
 250 #define TSEC2_PHYIDX            0
 251 #define TSEC1_FLAGS             TSEC_GIGABIT
 252 #define TSEC2_FLAGS             TSEC_GIGABIT
 253 #define CONFIG_ETHPRIME         "TSEC0"
 254
 255 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 256
 257 #define CONFIG_ETHER_ON_FCC2            /* define if ether on FCC   */
 258 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 259 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
 260
 261 #if (CONFIG_ETHER_INDEX == 2)
 262   /*
 263    * - Rx-CLK is CLK13
 264    * - Tx-CLK is CLK14
 265    * - Select bus for bd/buffers
 266    * - Full duplex
 267    */
 268   #define CONFIG_SYS_CMXFCR_MASK2       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 269   #define CONFIG_SYS_CMXFCR_VALUE2      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 270   #define CONFIG_SYS_CPMFCR_RAMTYPE     0
 271 #if 0
 272   #define CONFIG_SYS_FCC_PSMR           (FCC_PSMR_FDE)
 273 #else
 274   #define CONFIG_SYS_FCC_PSMR           0
 275 #endif
 276   #define FETH2_RST             0x01
 277 #elif (CONFIG_ETHER_INDEX == 3)
 278   /* need more definitions here for FE3 */
 279   #define FETH3_RST             0x80
 280 #endif                                  /* CONFIG_ETHER_INDEX */
 281
 282 /* MDIO is done through the TSEC0 control.
 283 */
 284 #define CONFIG_MII                      /* MII PHY management */
 285 #undef CONFIG_BITBANGMII                /* bit-bang MII PHY management  */
 286
 287 #endif
 288
 289 /* Environment - default config is in flash, see below */
 290 #if 0   /* in EEPROM */
 291 # define CONFIG_ENV_IS_IN_EEPROM        1
 292 # define CONFIG_ENV_OFFSET              0
 293 # define CONFIG_ENV_SIZE                2048
 294 #else   /* in flash */
 295 # define CONFIG_ENV_IS_IN_FLASH 1
 296 # ifdef CONFIG_STXSSA_4M
 297 #  define CONFIG_ENV_SECT_SIZE  0x20000
 298 # else  /* default configuration - 64 MiB flash */
 299 #  define CONFIG_ENV_SECT_SIZE  0x40000
 300 # endif
 301 # define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 302 # define CONFIG_ENV_SIZE                0x4000
 303 # define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 304 # define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
 305 #endif
 306
 307 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 308 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 309
 310 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
 311
 312
 313 /*
 314  * BOOTP options
 315  */
 316 #define CONFIG_BOOTP_BOOTFILESIZE
 317 #define CONFIG_BOOTP_BOOTPATH
 318 #define CONFIG_BOOTP_GATEWAY
 319 #define CONFIG_BOOTP_HOSTNAME
 320
 321
 322 /*
 323  * Command line configuration.
 324  */
 325 #include <config_cmd_default.h>
 326
 327 #define CONFIG_CMD_DATE
 328 #define CONFIG_CMD_DHCP
 329 #define CONFIG_CMD_EEPROM
 330 #define CONFIG_CMD_I2C
 331 #define CONFIG_CMD_NFS
 332 #define CONFIG_CMD_PING
 333 #define CONFIG_CMD_SNTP
 334 #define CONFIG_CMD_REGINFO
 335
 336 #if defined(CONFIG_PCI)
 337     #define CONFIG_CMD_PCI
 338 #endif
 339
 340 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 341     #define CONFIG_CMD_MII
 342 #endif
 343
 344 #if defined(CONFIG_SYS_RAMBOOT)
 345     #undef CONFIG_CMD_SAVEENV
 346     #undef CONFIG_CMD_LOADS
 347 #else
 348     #define CONFIG_CMD_ELF
 349 #endif
 350
 351
 352 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 353
 354 /*
 355  * Miscellaneous configurable options
 356  */
 357 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 358 #define CONFIG_SYS_PROMPT       "SSA=> "        /* Monitor Command Prompt       */
 359 #if defined(CONFIG_CMD_KGDB)
 360 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 361 #else
 362 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 363 #endif
 364 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 365 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 366 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 367 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 368
 369 /*
 370  * For booting Linux, the board info and command line data
 371  * have to be in the first 8 MB of memory, since this is
 372  * the maximum mapped by the Linux kernel during initialization.
 373  */
 374 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 375
 376 #if defined(CONFIG_CMD_KGDB)
 377 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 378 #endif
 379
 380 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 381 #define CONFIG_HAS_ETH0
 382 #define CONFIG_HAS_ETH1
 383 #define CONFIG_HAS_ETH2
 384 #endif
 385
 386 /*
 387  * Environment in EEPROM is compatible with different flash sector sizes,
 388  * but only little space is available, so we use a very simple setup.
 389  * With environment in flash, we use a more powerful default configuration.
 390  */
 391 #ifdef CONFIG_ENV_IS_IN_EEPROM          /* use restricted "standard" environment */
 392
 393 #define CONFIG_BAUDRATE         38400
 394
 395 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 396 #define CONFIG_BOOTCOMMAND      "bootm 0xffc00000 0xffd00000"
 397 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
 398 #define CONFIG_SERVERIP         192.168.85.1
 399 #define CONFIG_IPADDR           192.168.85.60
 400 #define CONFIG_GATEWAYIP        192.168.85.1
 401 #define CONFIG_NETMASK          255.255.255.0
 402 #define CONFIG_HOSTNAME         STX_SSA
 403 #define CONFIG_ROOTPATH         "/gppproot"
 404 #define CONFIG_BOOTFILE         "uImage"
 405 #define CONFIG_LOADADDR         0x1000000
 406
 407 #else /* ENV IS IN FLASH                -- use a full-blown envionment */
 408
 409 #define CONFIG_BAUDRATE         115200
 410
 411 #define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 412
 413 #define CONFIG_PREBOOT  "echo;" \
 414         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 415         "echo"
 416
 417 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 418
 419 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 420         "hostname=gp3ssa\0"                                             \
 421         "bootfile=/tftpboot/gp3ssa/uImage\0"                            \
 422         "loadaddr=400000\0"                                             \
 423         "netdev=eth0\0"                                                 \
 424         "consdev=ttyS1\0"                                               \
 425         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 426                 "nfsroot=$serverip:$rootpath\0"                         \
 427         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 428         "addip=setenv bootargs $bootargs "                              \
 429                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 430                 ":$hostname:$netdev:off panic=1\0"                      \
 431         "addcons=setenv bootargs $bootargs "                            \
 432                 "console=$consdev,$baudrate\0"                          \
 433         "flash_nfs=run nfsargs addip addcons;"                          \
 434                 "bootm $kernel_addr\0"                                  \
 435         "flash_self=run ramargs addip addcons;"                         \
 436                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 437         "net_nfs=tftp $loadaddr $bootfile;"                             \
 438                 "run nfsargs addip addcons;bootm\0"                     \
 439         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 440         "kernel_addr=FC000000\0"                                        \
 441         "ramdisk_addr=FC200000\0"                                       \
 442         ""
 443 #define CONFIG_BOOTCOMMAND      "run flash_self"
 444
 445 #endif  /* CONFIG_ENV_IS_IN_EEPROM */
 446
 447 #endif  /* __CONFIG_H */