include/configs/stxssa.h

   1 /*
   2  * (C) Copyright 2005 Embedded Alley Solutions, Inc.
   3  * Dan Malek <dan@embeddedalley.com>
   4  * Copied from STx GP3.
   5  * Updates for Silicon Tx GP3 SSA board.
   6  *
   7  * (C) Copyright 2002,2003 Motorola,Inc.
   8  * Xianghua Xiao <X.Xiao@motorola.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 /* mpc8560ads board configuration file */
  30 /* please refer to doc/README.mpc85xx for more info */
  31 /* make sure you change the MAC address and other network params first,
  32  * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /* High Level Configuration Options */
  39 #define CONFIG_BOOKE            1       /* BOOKE                */
  40 #define CONFIG_E500             1       /* BOOKE e500 family    */
  41 #define CONFIG_MPC85xx          1       /* MPC8540/MPC8560      */
  42 #define CONFIG_CPM2             1       /* has CPM2 */
  43 #define CONFIG_STXSSA           1       /* Silicon Tx GPPP SSA board specific*/
  44 #define CONFIG_MPC8560          1
  45
  46 #define CONFIG_SYS_TEXT_BASE    0xFFF80000
  47
  48 #define CONFIG_PCI                      /* PCI ethernet support */
  49 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  50 #define CONFIG_TSEC_ENET                /* tsec ethernet support*/
  51 #undef CONFIG_ETHER_ON_FCC              /* cpm FCC ethernet support */
  52 #define CONFIG_ENV_OVERWRITE
  53
  54 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  55
  56 /* sysclk for MPC85xx
  57  */
  58
  59 #define CONFIG_SYS_CLK_FREQ     33000000 /* most pci cards are 33Mhz */
  60
  61 /* Blinkin' LEDs for Robert :-)
  62 */
  63 #define CONFIG_SHOW_ACTIVITY 1
  64
  65 /*
  66  * These can be toggled for performance analysis, otherwise use default.
  67  */
  68 #define CONFIG_L2_CACHE                         /* toggle L2 cache             */
  69 #define  CONFIG_BTB                             /* toggle branch predition */
  70
  71 #define CONFIG_BOARD_EARLY_INIT_F   1           /* Call board_pre_init   */
  72
  73 #undef  CONFIG_SYS_DRAM_TEST                            /* memory test, takes time      */
  74 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  75 #define CONFIG_SYS_MEMTEST_END          0x00400000
  76
  77
  78 /* Localbus connector.  There are many options that can be
  79  * connected here, including sdram or lots of flash.
  80  * This address, however, is used to configure a 256M local bus
  81  * window that includes the Config latch below.
  82  */
  83 #define CONFIG_SYS_LBC_OPTION_BASE      0xF0000000      /* Localbus Extension */
  84 #define CONFIG_SYS_LBC_OPTION_SIZE      256             /* 256MB */
  85
  86 /* There are various flash options used, we configure for the largest,
  87  * which is 64Mbytes.  The CFI works fine and will discover the proper
  88  * sizes.
  89  */
  90 #ifdef CONFIG_STXSSA_4M
  91 #define CONFIG_SYS_FLASH_BASE           0xFFC00000      /* start of  4 MiB flash */
  92 #else
  93 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of 64 MiB flash */
  94 #endif
  95 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit      */
  96 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_FLASH_BASE | 0x0FF7)
  97
  98 #define CONFIG_SYS_FLASH_CFI            1
  99 #define CONFIG_FLASH_CFI_DRIVER 1
 100 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* use buffered writes (20x faster) */
 101 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip */
 102 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks   */
 103
 104 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 105
 106 #define CONFIG_SYS_FLASH_PROTECTION
 107
 108 /* The configuration latch is Chip Select 1.
 109  * It's an 8-bit latch in the lower 8 bits of the word.
 110  */
 111 #define CONFIG_SYS_LBC_CFGLATCH_BASE    0xFB000000      /* Base of config latch */
 112 #define CONFIG_SYS_BR1_PRELIM           0xFB001801      /* 32-bit port */
 113 #define CONFIG_SYS_OR1_PRELIM           0xFFFF0FF7      /* 64K is enough */
 114
 115 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
 116
 117 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 118 #define CONFIG_SYS_RAMBOOT
 119 #else
 120 #undef  CONFIG_SYS_RAMBOOT
 121 #endif
 122
 123 #ifdef CONFIG_SYS_RAMBOOT
 124 #define CONFIG_SYS_CCSRBAR_DEFAULT      0x40000000      /* CCSRBAR by BDI cfg   */
 125 #endif
 126
 127 #define CONFIG_SYS_CCSRBAR              0xe0000000
 128 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
 129
 130 /* DDR Setup */
 131 #define CONFIG_FSL_DDR1
 132 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
 133 #define CONFIG_DDR_SPD
 134 #undef CONFIG_FSL_DDR_INTERACTIVE
 135
 136 #undef  CONFIG_DDR_ECC                  /* only for ECC DDR module */
 137 #define CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
 138
 139 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 140
 141 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000      /* DDR is system memory*/
 142 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 143
 144 #define CONFIG_NUM_DDR_CONTROLLERS      1
 145 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 146 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 147
 148 /* I2C addresses of SPD EEPROMs */
 149 #define SPD_EEPROM_ADDRESS      0x54    /* CTLR 0 DIMM 0 */
 150
 151 #undef CONFIG_CLOCKS_IN_MHZ
 152
 153 /* local bus definitions */
 154 #define CONFIG_SYS_BR2_PRELIM           0xf8001861      /* 64MB localbus SDRAM  */
 155 #define CONFIG_SYS_OR2_PRELIM           0xfc006901
 156 #define CONFIG_SYS_LBC_LCRR             0x00030004      /* local bus freq       */
 157 #define CONFIG_SYS_LBC_LBCR             0x00000000
 158 #define CONFIG_SYS_LBC_LSRT             0x20000000
 159 #define CONFIG_SYS_LBC_MRTPR            0x20000000
 160 #define CONFIG_SYS_LBC_LSDMR_1          0x2861b723
 161 #define CONFIG_SYS_LBC_LSDMR_2          0x0861b723
 162 #define CONFIG_SYS_LBC_LSDMR_3          0x0861b723
 163 #define CONFIG_SYS_LBC_LSDMR_4          0x1861b723
 164 #define CONFIG_SYS_LBC_LSDMR_5          0x4061b723
 165
 166 #define CONFIG_SYS_INIT_RAM_LOCK        1
 167 #define CONFIG_SYS_INIT_RAM_ADDR        0x60000000      /* Initial RAM address  */
 168 #define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 169
 170 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 171 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 172
 173 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 174 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)    /* Reserved for malloc */
 175
 176 /* Serial Port */
 177 #define CONFIG_CONS_INDEX     2
 178 #define CONFIG_SYS_NS16550
 179 #define CONFIG_SYS_NS16550_SERIAL
 180 #define CONFIG_SYS_NS16550_REG_SIZE     1
 181 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 182
 183 #define CONFIG_SYS_BAUDRATE_TABLE  \
 184         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 185
 186 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 187 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 188
 189 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 190 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 191 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 192
 193 /* pass open firmware flat tree */
 194 #define CONFIG_OF_LIBFDT                1
 195 #define CONFIG_OF_BOARD_SETUP           1
 196 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 197
 198 /*
 199  * I2C
 200  */
 201 #define CONFIG_FSL_I2C                  /* Use FSL common I2C driver */
 202 #define  CONFIG_HARD_I2C                /* I2C with hardware support*/
 203 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 204 #define CONFIG_SYS_I2C_SLAVE            0x7F
 205 #undef CONFIG_SYS_I2C_NOPROBES
 206 #define CONFIG_SYS_I2C_OFFSET           0x3000
 207
 208 /* I2C RTC */
 209 #define CONFIG_RTC_DS1337               /* This is really a DS1339 RTC  */
 210 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 211
 212 /* I2C EEPROM.  AT24C32, we keep our environment in here.
 213 */
 214 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x51    /* 1010001x             */
 215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write  */
 217 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   20
 218
 219 /*
 220  * Standard 8555 PCI mapping.
 221  * Addresses are mapped 1-1.
 222  */
 223 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 224 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 225 #define CONFIG_SYS_PCI1_MEM_SIZE        0x20000000      /* 512M */
 226 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
 227 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
 228 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000      /* 16M */
 229
 230 #define CONFIG_SYS_PCI2_MEM_BASE        0xa0000000
 231 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 232 #define CONFIG_SYS_PCI2_MEM_SIZE        0x20000000      /* 512M */
 233 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
 234 #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
 235 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000      /* 16M */
 236
 237 #if defined(CONFIG_PCI)                 /* PCI Ethernet card */
 238 #define CONFIG_MPC85XX_PCI2     1
 239 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 240
 241 #define CONFIG_EEPRO100
 242 #define CONFIG_TULIP
 243
 244 #if !defined(CONFIG_PCI_PNP)
 245   #define PCI_ENET0_IOADDR      0xe0000000
 246   #define PCI_ENET0_MEMADDR     0xe0000000
 247   #define PCI_IDSEL_NUMBER      0x0c    /* slot0->3(IDSEL)=12->15 */
 248 #endif
 249
 250 #define CONFIG_PCI_SCAN_SHOW
 251 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057   /* Motorola */
 252
 253 #endif /* CONFIG_PCI */
 254
 255 #if defined(CONFIG_TSEC_ENET)
 256
 257 #define CONFIG_MII              1       /* MII PHY management           */
 258
 259 #define CONFIG_TSEC1    1
 260 #define CONFIG_TSEC1_NAME       "TSEC0"
 261 #define CONFIG_TSEC2    1
 262 #define CONFIG_TSEC2_NAME       "TSEC1"
 263
 264 #define TSEC1_PHY_ADDR          2
 265 #define TSEC2_PHY_ADDR          4
 266 #define TSEC1_PHYIDX            0
 267 #define TSEC2_PHYIDX            0
 268 #define TSEC1_FLAGS             TSEC_GIGABIT
 269 #define TSEC2_FLAGS             TSEC_GIGABIT
 270 #define CONFIG_ETHPRIME         "TSEC0"
 271
 272 #elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 273
 274 #define CONFIG_ETHER_ON_FCC2            /* define if ether on FCC   */
 275 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 276 #define CONFIG_ETHER_INDEX      2       /* which channel for ether  */
 277
 278 #if (CONFIG_ETHER_INDEX == 2)
 279   /*
 280    * - Rx-CLK is CLK13
 281    * - Tx-CLK is CLK14
 282    * - Select bus for bd/buffers
 283    * - Full duplex
 284    */
 285   #define CONFIG_SYS_CMXFCR_MASK2       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 286   #define CONFIG_SYS_CMXFCR_VALUE2      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 287   #define CONFIG_SYS_CPMFCR_RAMTYPE     0
 288 #if 0
 289   #define CONFIG_SYS_FCC_PSMR           (FCC_PSMR_FDE)
 290 #else
 291   #define CONFIG_SYS_FCC_PSMR           0
 292 #endif
 293   #define FETH2_RST             0x01
 294 #elif (CONFIG_ETHER_INDEX == 3)
 295   /* need more definitions here for FE3 */
 296   #define FETH3_RST             0x80
 297 #endif                                  /* CONFIG_ETHER_INDEX */
 298
 299 /* MDIO is done through the TSEC0 control.
 300 */
 301 #define CONFIG_MII                      /* MII PHY management */
 302 #undef CONFIG_BITBANGMII                /* bit-bang MII PHY management  */
 303
 304 #endif
 305
 306 /* Environment - default config is in flash, see below */
 307 #if 0   /* in EEPROM */
 308 # define CONFIG_ENV_IS_IN_EEPROM        1
 309 # define CONFIG_ENV_OFFSET              0
 310 # define CONFIG_ENV_SIZE                2048
 311 #else   /* in flash */
 312 # define CONFIG_ENV_IS_IN_FLASH 1
 313 # ifdef CONFIG_STXSSA_4M
 314 #  define CONFIG_ENV_SECT_SIZE  0x20000
 315 # else  /* default configuration - 64 MiB flash */
 316 #  define CONFIG_ENV_SECT_SIZE  0x40000
 317 # endif
 318 # define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 319 # define CONFIG_ENV_SIZE                0x4000
 320 # define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 321 # define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
 322 #endif
 323
 324 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 325 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 326
 327 #define CONFIG_TIMESTAMP                /* Print image info with ts     */
 328
 329
 330 /*
 331  * BOOTP options
 332  */
 333 #define CONFIG_BOOTP_BOOTFILESIZE
 334 #define CONFIG_BOOTP_BOOTPATH
 335 #define CONFIG_BOOTP_GATEWAY
 336 #define CONFIG_BOOTP_HOSTNAME
 337
 338
 339 /*
 340  * Command line configuration.
 341  */
 342 #include <config_cmd_default.h>
 343
 344 #define CONFIG_CMD_DATE
 345 #define CONFIG_CMD_DHCP
 346 #define CONFIG_CMD_EEPROM
 347 #define CONFIG_CMD_I2C
 348 #define CONFIG_CMD_NFS
 349 #define CONFIG_CMD_PING
 350 #define CONFIG_CMD_SNTP
 351 #define CONFIG_CMD_REGINFO
 352
 353 #if defined(CONFIG_PCI)
 354     #define CONFIG_CMD_PCI
 355 #endif
 356
 357 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 358     #define CONFIG_CMD_MII
 359 #endif
 360
 361 #if defined(CONFIG_SYS_RAMBOOT)
 362     #undef CONFIG_CMD_SAVEENV
 363     #undef CONFIG_CMD_LOADS
 364 #else
 365     #define CONFIG_CMD_ELF
 366 #endif
 367
 368
 369 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 370
 371 /*
 372  * Miscellaneous configurable options
 373  */
 374 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 375 #define CONFIG_SYS_PROMPT       "SSA=> "        /* Monitor Command Prompt       */
 376 #if defined(CONFIG_CMD_KGDB)
 377 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 378 #else
 379 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 380 #endif
 381 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 382 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 383 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 384 #define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 385 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 386
 387 /*
 388  * For booting Linux, the board info and command line data
 389  * have to be in the first 8 MB of memory, since this is
 390  * the maximum mapped by the Linux kernel during initialization.
 391  */
 392 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 393
 394 #if defined(CONFIG_CMD_KGDB)
 395 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 396 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 397 #endif
 398
 399 /*Note: change below for your network setting!!! */
 400 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 401 #define CONFIG_HAS_ETH0
 402 #define CONFIG_ETHADDR   00:e0:0c:07:9b:8a
 403 #define CONFIG_HAS_ETH1
 404 #define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
 405 #define CONFIG_HAS_ETH2
 406 #define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
 407 #endif
 408
 409 /*
 410  * Environment in EEPROM is compatible with different flash sector sizes,
 411  * but only little space is available, so we use a very simple setup.
 412  * With environment in flash, we use a more powerful default configuration.
 413  */
 414 #ifdef CONFIG_ENV_IS_IN_EEPROM          /* use restricted "standard" environment */
 415
 416 #define CONFIG_BAUDRATE         38400
 417
 418 #define CONFIG_BOOTDELAY        3       /* -1 disable autoboot */
 419 #define CONFIG_BOOTCOMMAND      "bootm 0xffc00000 0xffd00000"
 420 #define CONFIG_BOOTARGS         "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
 421 #define CONFIG_SERVERIP         192.168.85.1
 422 #define CONFIG_IPADDR           192.168.85.60
 423 #define CONFIG_GATEWAYIP        192.168.85.1
 424 #define CONFIG_NETMASK          255.255.255.0
 425 #define CONFIG_HOSTNAME         STX_SSA
 426 #define CONFIG_ROOTPATH         "/gppproot"
 427 #define CONFIG_BOOTFILE         "uImage"
 428 #define CONFIG_LOADADDR         0x1000000
 429
 430 #else /* ENV IS IN FLASH                -- use a full-blown envionment */
 431
 432 #define CONFIG_BAUDRATE         115200
 433
 434 #define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 435
 436 #define CONFIG_PREBOOT  "echo;" \
 437         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 438         "echo"
 439
 440 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs   */
 441
 442 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 443         "hostname=gp3ssa\0"                                             \
 444         "bootfile=/tftpboot/gp3ssa/uImage\0"                            \
 445         "loadaddr=400000\0"                                             \
 446         "netdev=eth0\0"                                                 \
 447         "consdev=ttyS1\0"                                               \
 448         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 449                 "nfsroot=$serverip:$rootpath\0"                         \
 450         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 451         "addip=setenv bootargs $bootargs "                              \
 452                 "ip=$ipaddr:$serverip:$gatewayip:$netmask"              \
 453                 ":$hostname:$netdev:off panic=1\0"                      \
 454         "addcons=setenv bootargs $bootargs "                            \
 455                 "console=$consdev,$baudrate\0"                          \
 456         "flash_nfs=run nfsargs addip addcons;"                          \
 457                 "bootm $kernel_addr\0"                                  \
 458         "flash_self=run ramargs addip addcons;"                         \
 459                 "bootm $kernel_addr $ramdisk_addr\0"                    \
 460         "net_nfs=tftp $loadaddr $bootfile;"                             \
 461                 "run nfsargs addip addcons;bootm\0"                     \
 462         "rootpath=/opt/eldk/ppc_85xx\0"                                 \
 463         "kernel_addr=FC000000\0"                                        \
 464         "ramdisk_addr=FC200000\0"                                       \
 465         ""
 466 #define CONFIG_BOOTCOMMAND      "run flash_self"
 467
 468 #endif  /* CONFIG_ENV_IS_IN_EEPROM */
 469
 470 #endif  /* __CONFIG_H */