include/configs/stxxtc.h

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
  10  * U-Boot port on STx XTc 8xx board
  11  * Mostly copied from Panto's NETTA2 board.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MPC875           1       /* This is a MPC875 CPU         */
  23 #define CONFIG_STXXTC           1       /* ...on a STx XTc  board       */
  24
  25 #define CONFIG_SYS_TEXT_BASE    0x40F00000
  26
  27 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  28 #undef  CONFIG_8xx_CONS_SMC2
  29 #undef  CONFIG_8xx_CONS_NONE
  30
  31 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115.2kbps */
  32
  33 #define CONFIG_XIN              10000000        /* 10 MHz input xtal */
  34
  35 /* Select one of few clock rates defined later in this file.
  36 */
  37 /* #define MPC8XX_HZ            50000000 */
  38 #define MPC8XX_HZ               66666666
  39
  40 #define CONFIG_8xx_GCLK_FREQ    MPC8XX_HZ
  41
  42 #if 0
  43 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  44 #else
  45 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  46 #endif
  47
  48 #undef  CONFIG_CLOCKS_IN_MHZ    /* clocks NOT passsed to Linux in MHz */
  49
  50 #undef  CONFIG_BOOTARGS
  51 #define CONFIG_BOOTCOMMAND                                                      \
  52         "tftpboot; "                                                            \
  53         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  54         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  55         "bootm"
  56
  57 #define CONFIG_SOURCE
  58 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  59 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  60
  61 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  62
  63 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  64 #define CONFIG_BOARD_SPECIFIC_LED       /* version has board specific leds */
  65
  66 /*
  67  * BOOTP options
  68  */
  69 #define CONFIG_BOOTP_SUBNETMASK
  70 #define CONFIG_BOOTP_GATEWAY
  71 #define CONFIG_BOOTP_HOSTNAME
  72 #define CONFIG_BOOTP_BOOTPATH
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74 #define CONFIG_BOOTP_NISDOMAIN
  75
  76
  77 #undef CONFIG_MAC_PARTITION
  78 #undef CONFIG_DOS_PARTITION
  79
  80 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  81
  82 #define FEC_ENET                1       /* eth.c needs it that way... */
  83 #undef CONFIG_SYS_DISCOVER_PHY
  84 #define CONFIG_MII              1
  85 #define CONFIG_MII_INIT         1
  86 #undef CONFIG_RMII
  87
  88 #define CONFIG_ETHER_ON_FEC1    1
  89 #define CONFIG_FEC1_PHY         1       /* phy address of FEC */
  90 #undef CONFIG_FEC1_PHY_NORXERR
  91
  92 #define CONFIG_ETHER_ON_FEC2    1
  93 #define CONFIG_FEC2_PHY         3
  94 #undef CONFIG_FEC2_PHY_NORXERR
  95
  96 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
  97
  98
  99 /*
 100  * Command line configuration.
 101  */
 102 #include <config_cmd_default.h>
 103
 104 #define CONFIG_CMD_DHCP
 105 #define CONFIG_CMD_MII
 106 #define CONFIG_CMD_NFS
 107 #define CONFIG_CMD_PING
 108
 109
 110 #define CONFIG_BOARD_EARLY_INIT_F       1
 111 #define CONFIG_MISC_INIT_R
 112
 113 /*
 114  * Miscellaneous configurable options
 115  */
 116 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 117 #define CONFIG_SYS_PROMPT       "xtc> "         /* Monitor Command Prompt       */
 118
 119 #define CONFIG_SYS_HUSH_PARSER  1
 120
 121 #if defined(CONFIG_CMD_KGDB)
 122 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 123 #else
 124 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 125 #endif
 126 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 127 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 128 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 129
 130 #define CONFIG_SYS_MEMTEST_START        0x0300000       /* memtest works on     */
 131 #define CONFIG_SYS_MEMTEST_END          0x0700000       /* 3 ... 7 MB in DRAM   */
 132
 133 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 134
 135 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 136
 137 /*
 138  * Low Level Configuration Settings
 139  * (address mappings, register initial values, etc.)
 140  * You should know what you are doing if you make changes here.
 141  */
 142 /*-----------------------------------------------------------------------
 143  * Internal Memory Mapped Register
 144  */
 145 #define CONFIG_SYS_IMMR         0xFF000000
 146
 147 /*-----------------------------------------------------------------------
 148  * Definitions for initial stack pointer and data area (in DPRAM)
 149  */
 150 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 151 #define CONFIG_SYS_INIT_RAM_SIZE        0x3000  /* Size of used area in DPRAM   */
 152 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 153 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 154
 155 /*-----------------------------------------------------------------------
 156  * Start addresses for the final memory configuration
 157  * (Set up by the startup code)
 158  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 159  */
 160 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 161 #define CONFIG_SYS_FLASH_BASE           0x40000000
 162 #if defined(DEBUG)
 163 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 164 #else
 165 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 166 #endif
 167
 168 /* yes this is weird, I know :) */
 169 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000)
 170 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 171
 172 #define CONFIG_SYS_RESET_ADDRESS        0x80000000
 173
 174 /*
 175  * For booting Linux, the board info and command line data
 176  * have to be in the first 8 MB of memory, since this is
 177  * the maximum mapped by the Linux kernel during initialization.
 178  */
 179 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 180
 181 /*-----------------------------------------------------------------------
 182  * FLASH organization
 183  */
 184 #define CONFIG_ENV_IS_IN_FLASH  1
 185 #define CONFIG_ENV_SECT_SIZE    0x10000
 186
 187 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00000000)
 188 #define CONFIG_ENV_OFFSET               0
 189 #define CONFIG_ENV_SIZE         0x4000
 190
 191 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_SYS_FLASH_BASE + 0x00010000)
 192 #define CONFIG_ENV_OFFSET_REDUND        0
 193 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 194
 195 #define CONFIG_SYS_FLASH_CFI            1
 196 #define CONFIG_FLASH_CFI_DRIVER 1
 197 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* use buffered writes (20x faster) */
 198 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip */
 199 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks   */
 200
 201 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
 202
 203 #define CONFIG_SYS_FLASH_PROTECTION
 204
 205 /*-----------------------------------------------------------------------
 206  * Cache Configuration
 207  */
 208 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs */
 209 #if defined(CONFIG_CMD_KGDB)
 210 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value */
 211 #endif
 212
 213 /*-----------------------------------------------------------------------
 214  * SYPCR - System Protection Control                            11-9
 215  * SYPCR can only be written once after reset!
 216  *-----------------------------------------------------------------------
 217  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 218  */
 219 #if defined(CONFIG_WATCHDOG)
 220 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 221                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 222 #else
 223 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 224 #endif
 225
 226 /*-----------------------------------------------------------------------
 227  * SIUMCR - SIU Module Configuration                            11-6
 228  *-----------------------------------------------------------------------
 229  * PCMCIA config., multi-function pin tri-state
 230  */
 231 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
 232
 233 /*-----------------------------------------------------------------------
 234  * TBSCR - Time Base Status and Control                         11-26
 235  *-----------------------------------------------------------------------
 236  * Clear Reference Interrupt Status, Timebase freezing enabled
 237  */
 238 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 239
 240 /*-----------------------------------------------------------------------
 241  * RTCSC - Real-Time Clock Status and Control Register          11-27
 242  *-----------------------------------------------------------------------
 243  */
 244 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 245
 246 /*-----------------------------------------------------------------------
 247  * PISCR - Periodic Interrupt Status and Control                11-31
 248  *-----------------------------------------------------------------------
 249  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 250  */
 251 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 252
 253 /*-----------------------------------------------------------------------
 254  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 255  *-----------------------------------------------------------------------
 256  * Reset PLL lock status sticky bit, timer expired status bit and timer
 257  * interrupt status bit
 258  *
 259  */
 260
 261 #if CONFIG_XIN == 10000000
 262
 263 #if MPC8XX_HZ == 50000000
 264 #define CONFIG_SYS_PLPRCR       ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 265                          (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 266                          PLPRCR_TEXPS)
 267 #elif MPC8XX_HZ == 66666666
 268 #define CONFIG_SYS_PLPRCR       ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
 269                          (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
 270                          PLPRCR_TEXPS)
 271 #else
 272 #error unsupported CPU freq for XIN = 10MHz
 273 #endif
 274 #else
 275 #error unsupported freq for XIN (must be 10MHz)
 276 #endif
 277
 278
 279 /*
 280  *-----------------------------------------------------------------------
 281  * SCCR - System Clock and reset Control Register               15-27
 282  *-----------------------------------------------------------------------
 283  * Set clock output, timebase and RTC source and divider,
 284  * power management and some other internal clocks
 285  *
 286  * Note: When TBS == 0 the timebase is independent of current cpu clock.
 287  */
 288
 289 #define SCCR_MASK       SCCR_EBDF11
 290 #if MPC8XX_HZ > 66666666
 291 #define CONFIG_SYS_SCCR (/* SCCR_TBS     | */ SCCR_CRQEN | \
 292                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 293                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 294                          SCCR_DFALCD00 | SCCR_EBDF01)
 295 #else
 296 #define CONFIG_SYS_SCCR (/* SCCR_TBS     | */ SCCR_CRQEN | \
 297                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 298                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 299                          SCCR_DFALCD00)
 300 #endif
 301
 302 /*-----------------------------------------------------------------------
 303  *
 304  *-----------------------------------------------------------------------
 305  *
 306  */
 307 /*#define       CONFIG_SYS_DER  0x2002000F*/
 308 #define CONFIG_SYS_DER  0
 309
 310 /*
 311  * Init Memory Controller:
 312  *
 313  * BR0/1 and OR0/1 (FLASH)
 314  */
 315
 316 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 317 #define FLASH_BASE1_PRELIM      0x42000000      /* FLASH bank #1        */
 318
 319 /* used to re-map FLASH both when starting from SRAM or FLASH:
 320  * restrict access enough to keep SRAM working (if any)
 321  * but not too much to meddle with FLASH accesses
 322  */
 323
 324 #define FLASH_BANK_MAX_SIZE     0x01000000      /* max size per chip */
 325
 326 #define CONFIG_SYS_REMAP_OR_AM          0x80000000
 327 #define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
 328
 329 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 330 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)
 331
 332 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 333 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 334 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 335
 336 #define CONFIG_SYS_OR1_PRELIM   ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
 337 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 338
 339 /*
 340  * BR4 and OR4 (SDRAM)
 341  *
 342  */
 343 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 344 #define SDRAM_MAX_SIZE          (256 << 20)     /* max 256MB per bank   */
 345
 346 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 347 #define CONFIG_SYS_OR_TIMING_SDRAM      (OR_CSNT_SAM | OR_G5LS)
 348
 349 #define CONFIG_SYS_OR4_PRELIM   ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
 350 #define CONFIG_SYS_BR4_PRELIM   ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
 351
 352 /*
 353  * Memory Periodic Timer Prescaler
 354  */
 355
 356 /*
 357  * Memory Periodic Timer Prescaler
 358  *
 359  * The Divider for PTA (refresh timer) configuration is based on an
 360  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 361  * the number of chip selects (NCS) and the actually needed refresh
 362  * rate is done by setting MPTPR.
 363  *
 364  * PTA is calculated from
 365  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 366  *
 367  *      gclk      CPU clock (not bus clock!)
 368  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 369  *
 370  * 4096  Rows from SDRAM example configuration
 371  * 1000  factor s -> ms
 372  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 373  *    4  Number of refresh cycles per period
 374  *   64  Refresh cycle in ms per number of rows
 375  * --------------------------------------------
 376  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 377  *
 378  * 50 MHz => 50.000.000 / Divider =  98
 379  * 66 Mhz => 66.000.000 / Divider = 129
 380  * 80 Mhz => 80.000.000 / Divider = 156
 381  */
 382
 383 #define CONFIG_SYS_MAMR_PTA              234
 384
 385 /*
 386  * For 16 MBit, refresh rates could be 31.3 us
 387  * (= 64 ms / 2K = 125 / quad bursts).
 388  * For a simpler initialization, 15.6 us is used instead.
 389  *
 390  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 391  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 392  */
 393 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 394 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 395
 396 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 397 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 398 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 399
 400 /*
 401  * MAMR settings for SDRAM
 402  */
 403
 404 /* 8 column SDRAM */
 405 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 406                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 407                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 408
 409 /* 9 column SDRAM */
 410 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 411                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 412                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 413
 414 #define CONFIG_LAST_STAGE_INIT          /* needed to reset the damn phys */
 415
 416 /****************************************************************/
 417
 418 #define NAND_SIZE       0x00010000      /* 64K */
 419 #define NAND_BASE       0xF1000000
 420
 421 /*****************************************************************************/
 422
 423 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 424
 425 /*****************************************************************************/
 426
 427 /* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
 428  * CxOE and CxRESET.  We use the CxOE.
 429  */
 430 #define STATUS_LED_BIT          0x00000080              /* bit 24 */
 431
 432 #define STATUS_LED_PERIOD       (CONFIG_SYS_HZ / 2)
 433 #define STATUS_LED_STATE        STATUS_LED_BLINKING
 434
 435 #define STATUS_LED_ACTIVE       0               /* LED on for bit == 0  */
 436 #define STATUS_LED_BOOT         0               /* LED 0 used for boot status */
 437
 438 #ifndef __ASSEMBLY__
 439
 440 /* LEDs */
 441
 442 /* led_id_t is unsigned int mask */
 443 typedef unsigned int led_id_t;
 444
 445 #define __led_toggle(_msk) \
 446         do { \
 447                 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
 448         } while(0)
 449
 450 #define __led_set(_msk, _st) \
 451         do { \
 452                 if ((_st)) \
 453                         ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
 454                 else \
 455                         ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
 456         } while(0)
 457
 458 #define __led_init(msk, st) __led_set(msk, st)
 459
 460 #endif
 461
 462 /******************************************************************************/
 463
 464 #define CONFIG_SYS_CONSOLE_IS_IN_ENV            1
 465 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE    1
 466 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE        1
 467
 468 /******************************************************************************/
 469
 470 /* use board specific hardware */
 471 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 472 #define CONFIG_HW_WATCHDOG
 473
 474 /*****************************************************************************/
 475
 476 #define CONFIG_AUTO_COMPLETE    1
 477 #define CONFIG_CRC32_VERIFY     1
 478 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE       1
 479
 480 /*****************************************************************************/
 481
 482 /* pass open firmware flattened device tree */
 483 #define CONFIG_OF_LIBFDT        1
 484
 485 #define OF_TBCLK                (MPC8XX_HZ / 16)
 486
 487 #endif  /* __CONFIG_H */