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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/t4qds.h
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * Corenet DS style board configuration file
13 #define CONFIG_CMD_REGINFO
15 /* High Level Configuration Options */
17 #define CONFIG_E500 /* BOOKE e500 family */
18 #define CONFIG_E500MC /* BOOKE e500mc family */
19 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
20 #define CONFIG_MP /* support multiple processors */
22 #ifndef CONFIG_SYS_TEXT_BASE
23 #define CONFIG_SYS_TEXT_BASE 0xeff40000
26 #ifndef CONFIG_RESET_VECTOR_ADDRESS
27 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
30 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
31 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
32 #define CONFIG_FSL_IFC /* Enable IFC Support */
33 #define CONFIG_PCIE1 /* PCIE controller 1 */
34 #define CONFIG_PCIE2 /* PCIE controller 2 */
35 #define CONFIG_PCIE3 /* PCIE controller 3 */
36 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
37 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
39 #define CONFIG_SYS_SRIO
40 #define CONFIG_SRIO1 /* SRIO port 1 */
41 #define CONFIG_SRIO2 /* SRIO port 2 */
43 #define CONFIG_ENV_OVERWRITE
46 * These can be toggled for performance analysis, otherwise use default.
48 #define CONFIG_SYS_CACHE_STASHING
49 #define CONFIG_BTB /* toggle branch predition */
51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
52 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
55 #define CONFIG_ENABLE_36BIT_PHYS
57 #define CONFIG_ADDR_MAP
58 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
61 #define CONFIG_SYS_MEMTEST_END 0x00400000
62 #define CONFIG_SYS_ALT_MEMTEST
63 #define CONFIG_PANIC_HANG /* do not reset board on panic */
66 * Config the L3 Cache as L3 SRAM
68 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
69 #define CONFIG_SYS_L3_SIZE (512 << 10)
70 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
71 #ifdef CONFIG_RAMBOOT_PBL
72 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
74 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
75 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
76 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
77 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
79 #define CONFIG_SYS_DCSRBAR 0xf0000000
80 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
85 #define CONFIG_VERY_BIG_RAM
86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
89 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
90 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
91 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
92 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
94 #define CONFIG_DDR_SPD
95 #define CONFIG_SYS_FSL_DDR3
100 #define CONFIG_SYS_FLASH_BASE 0xe0000000
101 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
103 #ifdef CONFIG_SPL_BUILD
104 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
106 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
109 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
110 #define CONFIG_MISC_INIT_R
112 #define CONFIG_HWCONFIG
114 /* define to use L1 as initial stack */
115 #define CONFIG_L1_INIT_RAM
116 #define CONFIG_SYS_INIT_RAM_LOCK
117 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
118 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
119 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
120 /* The assembler doesn't like typecast */
121 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
122 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
123 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
124 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
126 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
127 GENERATED_GBL_DATA_SIZE)
128 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
130 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
131 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
133 /* Serial Port - controlled on board with jumper J8
137 #define CONFIG_CONS_INDEX 1
138 #define CONFIG_SYS_NS16550_SERIAL
139 #define CONFIG_SYS_NS16550_REG_SIZE 1
140 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
142 #define CONFIG_SYS_BAUDRATE_TABLE \
143 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
145 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
146 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
147 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
148 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
151 #define CONFIG_SYS_I2C
152 #define CONFIG_SYS_I2C_FSL
153 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
154 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
155 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
156 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
161 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
162 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
163 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
165 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
166 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
167 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
171 * Memory space is mapped 1-1, but I/O space must start from 0.
174 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
175 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
176 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
177 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
178 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
179 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
180 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
181 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
182 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
184 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
185 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
186 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
187 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
188 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
189 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
190 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
191 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
192 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
194 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
195 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
196 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
197 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
198 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
199 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
200 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
201 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
202 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
204 /* controller 4, Base address 203000 */
205 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
206 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
207 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
208 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
209 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
210 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
213 #define CONFIG_PCI_INDIRECT_BRIDGE
215 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
216 #define CONFIG_DOS_PARTITION
217 #endif /* CONFIG_PCI */
220 #ifdef CONFIG_FSL_SATA_V2
221 #define CONFIG_LIBATA
222 #define CONFIG_FSL_SATA
224 #define CONFIG_SYS_SATA_MAX_DEVICE 2
226 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
227 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
229 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
230 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
233 #define CONFIG_CMD_SATA
234 #define CONFIG_DOS_PARTITION
237 #ifdef CONFIG_FMAN_ENET
238 #define CONFIG_MII /* MII PHY management */
239 #define CONFIG_ETHPRIME "FM1@DTSEC1"
240 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
246 #define CONFIG_LOADS_ECHO /* echo on for serial download */
247 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
250 * Command line configuration.
252 #define CONFIG_CMD_ERRATA
253 #define CONFIG_CMD_IRQ
256 #define CONFIG_CMD_PCI
260 * Miscellaneous configurable options
262 #define CONFIG_SYS_LONGHELP /* undef to save memory */
263 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
264 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
265 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
266 #ifdef CONFIG_CMD_KGDB
267 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
269 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
271 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
272 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
273 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
276 * For booting Linux, the board info and command line data
277 * have to be in the first 64 MB of memory, since this is
278 * the maximum mapped by the Linux kernel during initialization.
280 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
281 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
283 #ifdef CONFIG_CMD_KGDB
284 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
288 * Environment Configuration
290 #define CONFIG_ROOTPATH "/opt/nfsroot"
291 #define CONFIG_BOOTFILE "uImage"
292 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
294 /* default location for tftp and bootm */
295 #define CONFIG_LOADADDR 1000000
297 #define CONFIG_BAUDRATE 115200
299 #define CONFIG_HVBOOT \
300 "setenv bootargs config-addr=0x60000000; " \
301 "bootm 0x01000000 - 0x00f00000"
303 #endif /* __CONFIG_H */