include/configs/t4qds.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __T4QDS_H
  11 #define __T4QDS_H
  12
  13 /* High Level Configuration Options */
  14 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  15 #define CONFIG_MP                       /* support multiple processors */
  16
  17 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  19 #endif
  20
  21 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  22 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  23 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  24 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  25 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  26 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  27 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  28
  29 #define CONFIG_SYS_SRIO
  30 #define CONFIG_SRIO1                    /* SRIO port 1 */
  31 #define CONFIG_SRIO2                    /* SRIO port 2 */
  32
  33 #define CONFIG_ENV_OVERWRITE
  34
  35 /*
  36  * These can be toggled for performance analysis, otherwise use default.
  37  */
  38 #define CONFIG_SYS_CACHE_STASHING
  39 #define CONFIG_BTB                      /* toggle branch predition */
  40 #ifdef CONFIG_DDR_ECC
  41 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  42 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  43 #endif
  44
  45 #define CONFIG_ENABLE_36BIT_PHYS
  46
  47 #define CONFIG_ADDR_MAP
  48 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  49
  50 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  51 #define CONFIG_SYS_MEMTEST_END          0x00400000
  52 #define CONFIG_SYS_ALT_MEMTEST
  53
  54 /*
  55  *  Config the L3 Cache as L3 SRAM
  56  */
  57 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
  58 #define CONFIG_SYS_L3_SIZE              (512 << 10)
  59 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  60 #ifdef CONFIG_RAMBOOT_PBL
  61 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
  62 #endif
  63 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
  64 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
  65 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
  66 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
  67
  68 #define CONFIG_SYS_DCSRBAR              0xf0000000
  69 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  70
  71 /*
  72  * DDR Setup
  73  */
  74 #define CONFIG_VERY_BIG_RAM
  75 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  76 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  77
  78 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  79 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  80 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  81
  82 #define CONFIG_DDR_SPD
  83
  84 /*
  85  * IFC Definitions
  86  */
  87 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  88 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  89
  90 #ifdef CONFIG_SPL_BUILD
  91 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  92 #else
  93 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  94 #endif
  95
  96 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
  97 #define CONFIG_MISC_INIT_R
  98
  99 #define CONFIG_HWCONFIG
 100
 101 /* define to use L1 as initial stack */
 102 #define CONFIG_L1_INIT_RAM
 103 #define CONFIG_SYS_INIT_RAM_LOCK
 104 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 105 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 106 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 107 /* The assembler doesn't like typecast */
 108 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 109         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 110           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 111 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 112
 113 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 114                                         GENERATED_GBL_DATA_SIZE)
 115 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 116
 117 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 118 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 119
 120 /* Serial Port - controlled on board with jumper J8
 121  * open - index 2
 122  * shorted - index 1
 123  */
 124 #define CONFIG_CONS_INDEX       1
 125 #define CONFIG_SYS_NS16550_SERIAL
 126 #define CONFIG_SYS_NS16550_REG_SIZE     1
 127 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 128
 129 #define CONFIG_SYS_BAUDRATE_TABLE       \
 130         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 131
 132 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 133 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 134 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 135 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 136
 137 /* I2C */
 138 #define CONFIG_SYS_I2C
 139 #define CONFIG_SYS_I2C_FSL
 140 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 141 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 142 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 143 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 144
 145 /*
 146  * RapidIO
 147  */
 148 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 149 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 150 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 151
 152 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 153 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 154 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 155
 156 /*
 157  * General PCI
 158  * Memory space is mapped 1-1, but I/O space must start from 0.
 159  */
 160
 161 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 162 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 163 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 164 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 165 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 166 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 167 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 168 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 169 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 170
 171 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 172 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 173 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 174 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 175 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 176 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 177 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 178 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 179 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 180
 181 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 182 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 183 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 184 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 185 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 186 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 187 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 188 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 189 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 190
 191 /* controller 4, Base address 203000 */
 192 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 193 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 194 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 195 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 196 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 197 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 198
 199 #ifdef CONFIG_PCI
 200 #define CONFIG_PCI_INDIRECT_BRIDGE
 201
 202 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 203 #endif  /* CONFIG_PCI */
 204
 205 /* SATA */
 206 #ifdef CONFIG_FSL_SATA_V2
 207 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 208 #define CONFIG_SATA1
 209 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 210 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 211 #define CONFIG_SATA2
 212 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 213 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 214
 215 #define CONFIG_LBA48
 216 #endif
 217
 218 #ifdef CONFIG_FMAN_ENET
 219 #define CONFIG_MII              /* MII PHY management */
 220 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 221 #endif
 222
 223 /*
 224  * Environment
 225  */
 226 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 227 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 228
 229 /*
 230  * Command line configuration.
 231  */
 232
 233 /*
 234  * Miscellaneous configurable options
 235  */
 236 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 237 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 238 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 239 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 240
 241 /*
 242  * For booting Linux, the board info and command line data
 243  * have to be in the first 64 MB of memory, since this is
 244  * the maximum mapped by the Linux kernel during initialization.
 245  */
 246 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 247 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 248
 249 #ifdef CONFIG_CMD_KGDB
 250 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 251 #endif
 252
 253 /*
 254  * Environment Configuration
 255  */
 256 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 257 #define CONFIG_BOOTFILE         "uImage"
 258 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 259
 260 /* default location for tftp and bootm */
 261 #define CONFIG_LOADADDR         1000000
 262
 263 #define CONFIG_HVBOOT                           \
 264  "setenv bootargs config-addr=0x60000000; "     \
 265  "bootm 0x01000000 - 0x00f00000"
 266
 267 #endif  /* __CONFIG_H */