include/configs/t4qds.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Corenet DS style board configuration file
   9  */
  10 #ifndef __T4QDS_H
  11 #define __T4QDS_H
  12
  13 #define CONFIG_CMD_REGINFO
  14
  15 /* High Level Configuration Options */
  16 #define CONFIG_BOOKE
  17 #define CONFIG_E500                     /* BOOKE e500 family */
  18 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  19 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  20 #define CONFIG_MP                       /* support multiple processors */
  21
  22 #ifndef CONFIG_SYS_TEXT_BASE
  23 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  24 #endif
  25
  26 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  28 #endif
  29
  30 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  31 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  32 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  33 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  34 #define CONFIG_PCIE1                    /* PCIE controler 1 */
  35 #define CONFIG_PCIE2                    /* PCIE controler 2 */
  36 #define CONFIG_PCIE3                    /* PCIE controler 3 */
  37 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  38 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  39
  40 #define CONFIG_SYS_SRIO
  41 #define CONFIG_SRIO1                    /* SRIO port 1 */
  42 #define CONFIG_SRIO2                    /* SRIO port 2 */
  43
  44 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  45
  46 #define CONFIG_ENV_OVERWRITE
  47
  48 /*
  49  * These can be toggled for performance analysis, otherwise use default.
  50  */
  51 #define CONFIG_SYS_CACHE_STASHING
  52 #define CONFIG_BTB                      /* toggle branch predition */
  53 #ifdef CONFIG_DDR_ECC
  54 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  55 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  56 #endif
  57
  58 #define CONFIG_ENABLE_36BIT_PHYS
  59
  60 #define CONFIG_ADDR_MAP
  61 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  62
  63 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  64 #define CONFIG_SYS_MEMTEST_END          0x00400000
  65 #define CONFIG_SYS_ALT_MEMTEST
  66 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  67
  68 /*
  69  *  Config the L3 Cache as L3 SRAM
  70  */
  71 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  72
  73 #define CONFIG_SYS_DCSRBAR              0xf0000000
  74 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  75
  76 /*
  77  * DDR Setup
  78  */
  79 #define CONFIG_VERY_BIG_RAM
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  81 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  82
  83 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
  84 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  85 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  86 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  87
  88 #define CONFIG_DDR_SPD
  89 #define CONFIG_SYS_FSL_DDR3
  90
  91
  92 /*
  93  * IFC Definitions
  94  */
  95 #define CONFIG_SYS_FLASH_BASE   0xe0000000
  96 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  97
  98
  99 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 100
 101 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 102 #define CONFIG_MISC_INIT_R
 103
 104 #define CONFIG_HWCONFIG
 105
 106 /* define to use L1 as initial stack */
 107 #define CONFIG_L1_INIT_RAM
 108 #define CONFIG_SYS_INIT_RAM_LOCK
 109 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 110 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 111 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe0ec000
 112 /* The assembler doesn't like typecast */
 113 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 114         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 115           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 116 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 117
 118 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 119                                         GENERATED_GBL_DATA_SIZE)
 120 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 121
 122 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 123 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 124
 125 /* Serial Port - controlled on board with jumper J8
 126  * open - index 2
 127  * shorted - index 1
 128  */
 129 #define CONFIG_CONS_INDEX       1
 130 #define CONFIG_SYS_NS16550
 131 #define CONFIG_SYS_NS16550_SERIAL
 132 #define CONFIG_SYS_NS16550_REG_SIZE     1
 133 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 134
 135 #define CONFIG_SYS_BAUDRATE_TABLE       \
 136         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 137
 138 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 139 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 140 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 141 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 142
 143 /* Use the HUSH parser */
 144 #define CONFIG_SYS_HUSH_PARSER
 145 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 146
 147 /* pass open firmware flat tree */
 148 #define CONFIG_OF_LIBFDT
 149 #define CONFIG_OF_BOARD_SETUP
 150 #define CONFIG_OF_STDOUT_VIA_ALIAS
 151
 152 /* new uImage format support */
 153 #define CONFIG_FIT
 154 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 155
 156 /* I2C */
 157 #define CONFIG_SYS_I2C
 158 #define CONFIG_SYS_I2C_FSL
 159 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 160 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 161 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 162 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x118100
 163
 164 /*
 165  * RapidIO
 166  */
 167 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 168 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 169 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 170
 171 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 172 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 173 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 174
 175 /*
 176  * General PCI
 177  * Memory space is mapped 1-1, but I/O space must start from 0.
 178  */
 179
 180 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 181 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 182 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 183 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 184 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 185 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 186 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 187 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 188 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 189
 190 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 191 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 192 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 193 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 194 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 195 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 196 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 197 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 198 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 199
 200 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 201 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 202 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 203 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 204 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 205 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 206 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 207 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 208 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 209
 210 /* controller 4, Base address 203000 */
 211 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 212 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 213 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 214 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 215 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 216 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 217
 218 #ifdef CONFIG_PCI
 219 #define CONFIG_PCI_INDIRECT_BRIDGE
 220 #define CONFIG_NET_MULTI
 221 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 222 #define CONFIG_E1000
 223
 224 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 225 #define CONFIG_DOS_PARTITION
 226 #endif  /* CONFIG_PCI */
 227
 228 /* SATA */
 229 #ifdef CONFIG_FSL_SATA_V2
 230 #define CONFIG_LIBATA
 231 #define CONFIG_FSL_SATA
 232
 233 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 234 #define CONFIG_SATA1
 235 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 236 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 237 #define CONFIG_SATA2
 238 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 239 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 240
 241 #define CONFIG_LBA48
 242 #define CONFIG_CMD_SATA
 243 #define CONFIG_DOS_PARTITION
 244 #define CONFIG_CMD_EXT2
 245 #endif
 246
 247 #ifdef CONFIG_FMAN_ENET
 248 #define CONFIG_MII              /* MII PHY management */
 249 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 250 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 251 #endif
 252
 253 /*
 254  * Environment
 255  */
 256 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 257 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 258
 259 /*
 260  * Command line configuration.
 261  */
 262 #include <config_cmd_default.h>
 263
 264 #define CONFIG_CMD_DHCP
 265 #define CONFIG_CMD_ELF
 266 #define CONFIG_CMD_ERRATA
 267 #define CONFIG_CMD_GREPENV
 268 #define CONFIG_CMD_IRQ
 269 #define CONFIG_CMD_I2C
 270 #define CONFIG_CMD_MII
 271 #define CONFIG_CMD_PING
 272 #define CONFIG_CMD_SETEXPR
 273
 274 #ifdef CONFIG_PCI
 275 #define CONFIG_CMD_PCI
 276 #define CONFIG_CMD_NET
 277 #endif
 278
 279 /*
 280  * Miscellaneous configurable options
 281  */
 282 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 283 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 284 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 285 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 286 #ifdef CONFIG_CMD_KGDB
 287 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 288 #else
 289 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 290 #endif
 291 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 292 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 293 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 294
 295 /*
 296  * For booting Linux, the board info and command line data
 297  * have to be in the first 64 MB of memory, since this is
 298  * the maximum mapped by the Linux kernel during initialization.
 299  */
 300 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 301 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 302
 303 #ifdef CONFIG_CMD_KGDB
 304 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 305 #endif
 306
 307 /*
 308  * Environment Configuration
 309  */
 310 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 311 #define CONFIG_BOOTFILE         "uImage"
 312 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 313
 314 /* default location for tftp and bootm */
 315 #define CONFIG_LOADADDR         1000000
 316
 317
 318 #define CONFIG_BAUDRATE 115200
 319
 320 #define CONFIG_HVBOOT                           \
 321  "setenv bootargs config-addr=0x60000000; "     \
 322  "bootm 0x01000000 - 0x00f00000"
 323
 324 #endif  /* __CONFIG_H */