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1 /*
2 * Copyright (C) 2011
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * Copyright (C) 2009 TechNexion Ltd.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #ifndef __TAM3517_H
11 #define __TAM3517_H
12
13 /*
14 * High Level Configuration Options
15 */
16 #define CONFIG_OMAP /* in a TI OMAP core */
17 #define CONFIG_OMAP_GPIO
18 #define CONFIG_OMAP_COMMON
19 /* Common ARM Erratas */
20 #define CONFIG_ARM_ERRATA_454179
21 #define CONFIG_ARM_ERRATA_430973
22 #define CONFIG_ARM_ERRATA_621766
23
24 #define CONFIG_SYS_TEXT_BASE 0x80008000
25
26 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
27
28 #include <asm/arch/cpu.h> /* get chip and board defs */
29 #include <asm/arch/omap.h>
30
31 /*
32 * Display CPU and Board information
33 */
34 #define CONFIG_DISPLAY_CPUINFO
35 #define CONFIG_DISPLAY_BOARDINFO
36
37 /* Clock Defines */
38 #define V_OSCK 26000000 /* Clock output from T2 */
39 #define V_SCLK (V_OSCK >> 1)
40
41 #define CONFIG_MISC_INIT_R
42
43 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
44 #define CONFIG_SETUP_MEMORY_TAGS
45 #define CONFIG_INITRD_TAG
46 #define CONFIG_REVISION_TAG
47
48 /*
49 * Size of malloc() pool
50 */
51 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
52 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
53 2 * 1024 * 1024)
54 /*
55 * DDR related
56 */
57 #define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
58 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
59
60 /*
61 * Hardware drivers
62 */
63
64 /*
65 * NS16550 Configuration
66 */
67 #define CONFIG_SYS_NS16550_SERIAL
68 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
69 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
70
71 /*
72 * select serial console configuration
73 */
74 #define CONFIG_CONS_INDEX 1
75 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
76 #define CONFIG_SERIAL1 /* UART1 */
77
78 /* allow to overwrite serial and ethaddr */
79 #define CONFIG_ENV_OVERWRITE
80 #define CONFIG_BAUDRATE 115200
81 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
82 115200}
83 #define CONFIG_MMC
84 #define CONFIG_OMAP_HSMMC
85 #define CONFIG_GENERIC_MMC
86 #define CONFIG_DOS_PARTITION
87
88 /* EHCI */
89 #define CONFIG_OMAP3_GPIO_5
90 #define CONFIG_USB_EHCI
91 #define CONFIG_USB_EHCI_OMAP
92 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
93 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
94 #define CONFIG_USB_STORAGE
95
96 /* commands to include */
97 #define CONFIG_CMD_NAND /* NAND support */
98 #define CONFIG_CMD_EEPROM
99
100 #define CONFIG_SYS_NO_FLASH
101 #define CONFIG_SYS_I2C
102 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000
103 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
104 #define CONFIG_SYS_I2C_OMAP34XX
105 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
106 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
107 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
108
109 /*
110 * Board NAND Info.
111 */
112 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
113 /* to access */
114 /* nand at CS0 */
115
116 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
117 /* NAND devices */
118
119 #define CONFIG_AUTO_COMPLETE
120
121 /*
122 * Miscellaneous configurable options
123 */
124 #define CONFIG_SYS_LONGHELP /* undef to save memory */
125 #define CONFIG_CMDLINE_EDITING
126 #define CONFIG_AUTO_COMPLETE
127 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
128
129 /* Print Buffer Size */
130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
131 sizeof(CONFIG_SYS_PROMPT) + 16)
132 #define CONFIG_SYS_MAXARGS 32 /* max number of command */
133 /* args */
134 /* Boot Argument Buffer Size */
135 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
136 /* memtest works on */
137 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
138 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
139 0x01F00000) /* 31MB */
140
141 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
142 /* address */
143
144 /*
145 * AM3517 has 12 GP timers, they can be driven by the system clock
146 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
147 * This rate is divided by a local divisor.
148 */
149 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
150 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
151
152 /*
153 * Physical Memory Map
154 */
155 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
156 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
157 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
158
159 /*
160 * FLASH and environment organization
161 */
162
163 /* **** PISMO SUPPORT *** */
164 #define CONFIG_NAND
165 #define CONFIG_NAND_OMAP_GPMC
166 #define CONFIG_ENV_IS_IN_NAND
167 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
168
169 /* Redundant Environment */
170 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
171 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
172 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
173 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
174 2 * CONFIG_SYS_ENV_SECT_SIZE)
175 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
176
177 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
178 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
179 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
180 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
181 CONFIG_SYS_INIT_RAM_SIZE - \
182 GENERATED_GBL_DATA_SIZE)
183
184 /*
185 * ethernet support, EMAC
186 *
187 */
188 #define CONFIG_DRIVER_TI_EMAC
189 #define CONFIG_DRIVER_TI_EMAC_USE_RMII
190 #define CONFIG_MII
191 #define CONFIG_EMAC_MDIO_PHY_NUM 0
192 #define CONFIG_BOOTP_DNS
193 #define CONFIG_BOOTP_DNS2
194 #define CONFIG_BOOTP_SEND_HOSTNAME
195 #define CONFIG_NET_RETRY_COUNT 10
196
197 /* Defines for SPL */
198 #define CONFIG_SPL_FRAMEWORK
199 #define CONFIG_SPL_BOARD_INIT
200 #define CONFIG_SPL_CONSOLE
201 #define CONFIG_SPL_NAND_SIMPLE
202 #define CONFIG_SPL_NAND_SOFTECC
203 #define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
204
205 #define CONFIG_SPL_LIBCOMMON_SUPPORT
206 #define CONFIG_SPL_LIBDISK_SUPPORT
207 #define CONFIG_SPL_I2C_SUPPORT
208 #define CONFIG_SPL_MMC_SUPPORT
209 #define CONFIG_SPL_FAT_SUPPORT
210 #define CONFIG_SPL_LIBGENERIC_SUPPORT
211 #define CONFIG_SPL_SERIAL_SUPPORT
212 #define CONFIG_SPL_GPIO_SUPPORT
213 #define CONFIG_SPL_POWER_SUPPORT
214 #define CONFIG_SPL_NAND_SUPPORT
215 #define CONFIG_SPL_NAND_BASE
216 #define CONFIG_SPL_NAND_DRIVERS
217 #define CONFIG_SPL_NAND_ECC
218 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
219
220 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
221 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
222 CONFIG_SPL_TEXT_BASE)
223 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
224
225 #define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
226 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
227 #define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
228 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
229
230 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
231 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
232 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
233
234 /* FAT */
235 #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
236 #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
237
238 /* RAW SD card / eMMC */
239 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
240 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
241 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
242
243 /* NAND boot config */
244 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
245 #define CONFIG_SYS_NAND_PAGE_COUNT 64
246 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
247 #define CONFIG_SYS_NAND_OOBSIZE 64
248 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
249 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
250 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
251 #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
252 48, 49, 50, 51, 52, 53, 54, 55,\
253 56, 57, 58, 59, 60, 61, 62, 63}
254 #define CONFIG_SYS_NAND_ECCSIZE 256
255 #define CONFIG_SYS_NAND_ECCBYTES 3
256 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
257 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
258
259 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
260
261 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
262 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
263
264 #define CONFIG_CMD_UBI
265 #define CONFIG_CMD_UBIFS
266 #define CONFIG_RBTREE
267 #define CONFIG_LZO
268 #define CONFIG_MTD_PARTITIONS
269 #define CONFIG_MTD_DEVICE
270 #define CONFIG_CMD_MTDPARTS
271
272 /* Setup MTD for NAND on the SOM */
273 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
274 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
275 "1m(u-boot),256k(env1)," \
276 "256k(env2),6m(kernel),-(rootfs)"
277
278 #define CONFIG_TAM3517_SETTINGS \
279 "netdev=eth0\0" \
280 "nandargs=setenv bootargs root=${nandroot} " \
281 "rootfstype=${nandrootfstype}\0" \
282 "nfsargs=setenv bootargs root=/dev/nfs rw " \
283 "nfsroot=${serverip}:${rootpath}\0" \
284 "ramargs=setenv bootargs root=/dev/ram rw\0" \
285 "addip_sta=setenv bootargs ${bootargs} " \
286 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
287 ":${hostname}:${netdev}:off panic=1\0" \
288 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
289 "addip=if test -n ${ipdyn};then run addip_dyn;" \
290 "else run addip_sta;fi\0" \
291 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
292 "addtty=setenv bootargs ${bootargs}" \
293 " console=ttyO0,${baudrate}\0" \
294 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
295 "loadaddr=82000000\0" \
296 "kernel_addr_r=82000000\0" \
297 "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
298 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
299 "flash_self=run ramargs addip addtty addmtd addmisc;" \
300 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
301 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
302 "bootm ${kernel_addr}\0" \
303 "nandboot=run nandargs addip addtty addmtd addmisc;" \
304 "nand read ${kernel_addr_r} kernel\0" \
305 "bootm ${kernel_addr_r}\0" \
306 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
307 "run nfsargs addip addtty addmtd addmisc;" \
308 "bootm ${kernel_addr_r}\0" \
309 "net_self=if run net_self_load;then " \
310 "run ramargs addip addtty addmtd addmisc;" \
311 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
312 "else echo Images not loades;fi\0" \
313 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
314 "load=tftp ${loadaddr} ${u-boot}\0" \
315 "loadmlo=tftp ${loadaddr} ${mlo}\0" \
316 "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
317 "uboot_addr=0x80000\0" \
318 "update=nandecc sw;nand erase ${uboot_addr} 100000;" \
319 "nand write ${loadaddr} ${uboot_addr} 80000\0" \
320 "updatemlo=nandecc hw;nand erase 0 20000;" \
321 "nand write ${loadaddr} 0 20000\0" \
322 "upd=if run load;then echo Updating u-boot;if run update;" \
323 "then echo U-Boot updated;" \
324 "else echo Error updating u-boot !;" \
325 "echo Board without bootloader !!;" \
326 "fi;" \
327 "else echo U-Boot not downloaded..exiting;fi\0" \
328
329 /*
330 * this is common code for all TAM3517 boards.
331 * MAC address is stored from manufacturer in
332 * I2C EEPROM
333 */
334 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
335 /*
336 * The I2C EEPROM on the TAM3517 contains
337 * mac address and production data
338 */
339 struct tam3517_module_info {
340 char customer[48];
341 char product[48];
342
343 /*
344 * bit 0~47 : sequence number
345 * bit 48~55 : week of year, from 0.
346 * bit 56~63 : year
347 */
348 unsigned long long sequence_number;
349
350 /*
351 * bit 0~7 : revision fixed
352 * bit 8~15 : revision major
353 * bit 16~31 : TNxxx
354 */
355 unsigned int revision;
356 unsigned char eth_addr[4][8];
357 unsigned char _rev[100];
358 };
359
360 #define TAM3517_READ_EEPROM(info, ret) \
361 do { \
362 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
363 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
364 (void *)info, sizeof(*info))) \
365 ret = 1; \
366 else \
367 ret = 0; \
368 } while (0)
369
370 #define TAM3517_READ_MAC_FROM_EEPROM(info) \
371 do { \
372 char buf[80], ethname[20]; \
373 int i; \
374 memset(buf, 0, sizeof(buf)); \
375 for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
376 sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
377 (info)->eth_addr[i][5], \
378 (info)->eth_addr[i][4], \
379 (info)->eth_addr[i][3], \
380 (info)->eth_addr[i][2], \
381 (info)->eth_addr[i][1], \
382 (info)->eth_addr[i][0]); \
383 \
384 if (i) \
385 sprintf(ethname, "eth%daddr", i); \
386 else \
387 strcpy(ethname, "ethaddr"); \
388 printf("Setting %s from EEPROM with %s\n", ethname, buf);\
389 setenv(ethname, buf); \
390 } \
391 } while (0)
392
393 /* The following macros are taken from Technexion's documentation */
394 #define TAM3517_sequence_number(info) \
395 ((info)->sequence_number % 0x1000000000000LL)
396 #define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
397 #define TAM3517_year(info) ((info)->sequence_number >> 56)
398 #define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
399 #define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
400 #define TAM3517_revision_tn(info) ((info)->revision >> 16)
401
402 #define TAM3517_PRINT_SOM_INFO(info) \
403 do { \
404 printf("Vendor:%s\n", (info)->customer); \
405 printf("SOM: %s\n", (info)->product); \
406 printf("SeqNr: %02llu%02llu%012llu\n", \
407 TAM3517_year(info), \
408 TAM3517_week_of_year(info), \
409 TAM3517_sequence_number(info)); \
410 printf("Rev: TN%u %u.%u\n", \
411 TAM3517_revision_tn(info), \
412 TAM3517_revision_major(info), \
413 TAM3517_revision_fixed(info)); \
414 } while (0)
415
416 #endif
417
418 #endif /* __TAM3517_H */