include/configs/tao3530.h

   1 /*
   2  * Configuration settings for the TechNexion TAO-3530 SOM
   3  * equipped on Thunder baseboard.
   4  *
   5  * Edward Lin <linuxfae@technexion.com>
   6  * Tapani Utriainen <linuxfae@technexion.com>
   7  *
   8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19
  20 #define CONFIG_SDRC                     /* Has an SDRC controller */
  21
  22 #include <asm/arch/cpu.h>               /* get chip and board defs */
  23 #include <asm/arch/omap.h>
  24
  25 /* Clock Defines */
  26 #define V_OSCK                  26000000        /* Clock output from T2 */
  27 #define V_SCLK                  (V_OSCK >> 1)
  28
  29 #define CONFIG_MISC_INIT_R
  30
  31 #define CONFIG_CMDLINE_TAG
  32 #define CONFIG_SETUP_MEMORY_TAGS
  33 #define CONFIG_INITRD_TAG
  34 #define CONFIG_REVISION_TAG
  35
  36 /*
  37  * Size of malloc() pool
  38  */
  39 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)
  40 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  41
  42 /*
  43  * Hardware drivers
  44  */
  45
  46 /*
  47  * NS16550 Configuration
  48  */
  49 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  50
  51 #define CONFIG_SYS_NS16550_SERIAL
  52 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  53 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  54
  55 /*
  56  * select serial console configuration
  57  */
  58 #define CONFIG_CONS_INDEX               3
  59 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  60
  61 /* allow to overwrite serial and ethaddr */
  62 #define CONFIG_ENV_OVERWRITE
  63
  64 /* commands to include */
  65 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
  66 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  67 #define MTDIDS_DEFAULT                  "nand0=nand"
  68 #define MTDPARTS_DEFAULT                "mtdparts=nand:512k(x-loader),"\
  69                                         "1920k(u-boot),128k(u-boot-env),"\
  70                                         "4m(kernel),-(fs)"
  71
  72 #define CONFIG_CMD_NAND         /* NAND support                 */
  73
  74 #define CONFIG_SYS_I2C
  75 #define CONFIG_SYS_I2C_OMAP34XX
  76 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
  77 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
  78 #define CONFIG_I2C_MULTI_BUS
  79
  80 /*
  81  * TWL4030
  82  */
  83 #define CONFIG_TWL4030_LED
  84
  85 /*
  86  * Board NAND Info.
  87  */
  88 #define CONFIG_NAND_OMAP_GPMC
  89 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
  90                                                         /* to access nand */
  91 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  92                                                         /* to access nand at */
  93                                                         /* CS0 */
  94
  95 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  96                                                         /* devices */
  97 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
  98 /* Environment information */
  99
 100 #define CONFIG_EXTRA_ENV_SETTINGS \
 101         "loadaddr=0x82000000\0" \
 102         "console=ttyO2,115200n8\0" \
 103         "mpurate=600\0" \
 104         "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
 105         "tv_mode=omapfb.mode=tv:ntsc\0" \
 106         "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
 107         "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
 108         "extra_options= \0" \
 109         "mmcdev=0\0" \
 110         "mmcroot=/dev/mmcblk0p2 rw\0" \
 111         "mmcrootfstype=ext3 rootwait\0" \
 112         "nandroot=ubi0:rootfs ubi.mtd=4\0" \
 113         "nandrootfstype=ubifs\0" \
 114         "mmcargs=setenv bootargs console=${console} " \
 115                 "mpurate=${mpurate} " \
 116                 "${video_mode} " \
 117                 "root=${mmcroot} " \
 118                 "rootfstype=${mmcrootfstype} " \
 119                 "${extra_options}\0" \
 120         "nandargs=setenv bootargs console=${console} " \
 121                 "mpurate=${mpurate} " \
 122                 "${video_mode} " \
 123                 "${network_setting} " \
 124                 "root=${nandroot} " \
 125                 "rootfstype=${nandrootfstype} "\
 126                 "${extra_options}\0" \
 127         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 128         "bootscript=echo Running bootscript from mmc ...; " \
 129                 "source ${loadaddr}\0" \
 130         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 131         "mmcboot=echo Booting from mmc ...; " \
 132                 "run mmcargs; " \
 133                 "bootm ${loadaddr}\0" \
 134         "nandboot=echo Booting from nand ...; " \
 135                 "run nandargs; " \
 136                 "nand read ${loadaddr} 280000 400000; " \
 137                 "bootm ${loadaddr}\0" \
 138
 139 #define CONFIG_BOOTCOMMAND \
 140         "if mmc rescan ${mmcdev}; then " \
 141                 "if run loadbootscript; then " \
 142                         "run bootscript; " \
 143                 "else " \
 144                         "if run loaduimage; then " \
 145                                 "run mmcboot; " \
 146                         "else run nandboot; " \
 147                         "fi; " \
 148                 "fi; " \
 149         "else run nandboot; fi"
 150
 151 /*
 152  * Miscellaneous configurable options
 153  */
 154 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 155 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 156
 157 /* turn on command-line edit/hist/auto */
 158 #define CONFIG_CMDLINE_EDITING
 159 #define CONFIG_AUTO_COMPLETE
 160
 161 /* Print Buffer Size */
 162 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 163                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 164 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 165 /* Boot Argument Buffer Size */
 166 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 167
 168 #define CONFIG_SYS_ALT_MEMTEST          1
 169 #define CONFIG_SYS_MEMTEST_START        (0x82000000)            /* memtest */
 170                                                                 /* defaults */
 171 #define CONFIG_SYS_MEMTEST_END          (0x83FFFFFF)            /* 64MB */
 172 #define CONFIG_SYS_MEMTEST_SCRATCH      (0x81000000)    /* dummy address */
 173
 174 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 175                                                         /* load address */
 176 #define CONFIG_SYS_TEXT_BASE            0x80008000
 177
 178 /*
 179  * OMAP3 has 12 GP timers, they can be driven by the system clock
 180  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 181  * This rate is divided by a local divisor.
 182  */
 183 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 184 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 185
 186 /*
 187  * Physical Memory Map
 188  */
 189 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 190 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 191 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 192 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 193
 194 /*
 195  * FLASH and environment organization
 196  */
 197
 198 /* **** PISMO SUPPORT *** */
 199 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 200 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 201
 202 /* Monitor at start of flash */
 203 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 204 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 205
 206 #define CONFIG_ENV_IS_IN_NAND           1
 207 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 208 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 209
 210 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)
 211 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 212 #define CONFIG_ENV_ADDR                 CONFIG_ENV_OFFSET
 213
 214 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 215 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 216 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 217 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 218                                          CONFIG_SYS_INIT_RAM_SIZE - \
 219                                          GENERATED_GBL_DATA_SIZE)
 220
 221 #define CONFIG_OMAP3_SPI
 222
 223 /*
 224  * USB
 225  *
 226  * Currently only EHCI is enabled, the MUSB OTG controller
 227  * is not enabled.
 228  */
 229
 230 /* USB EHCI */
 231 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        162
 232
 233 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 234 #define CONFIG_USB_HOST_ETHER
 235 #define CONFIG_USB_ETHER_SMSC95XX
 236
 237 #define CONFIG_USB_ETHER
 238 #define CONFIG_USB_ETHER_RNDIS
 239
 240 /* Defines for SPL */
 241 #define CONFIG_SPL_FRAMEWORK
 242 #define CONFIG_SPL_NAND_SIMPLE
 243
 244 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 245 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 246
 247 #define CONFIG_SPL_BOARD_INIT
 248 #define CONFIG_SPL_NAND_BASE
 249 #define CONFIG_SPL_NAND_DRIVERS
 250 #define CONFIG_SPL_NAND_ECC
 251 #define CONFIG_SPL_OMAP3_ID_NAND
 252 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 253
 254 /* NAND boot config */
 255 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 256 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 257 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 258 #define CONFIG_SYS_NAND_OOBSIZE         64
 259 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 260 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 261 /*
 262  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 263  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 264  */
 265 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 266                                          10, 11, 12, 13 }
 267 #define CONFIG_SYS_NAND_ECCSIZE         512
 268 #define CONFIG_SYS_NAND_ECCBYTES        3
 269 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 270
 271 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 272 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 273
 274 #define CONFIG_SPL_TEXT_BASE            0x40200800
 275 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 276                                          CONFIG_SPL_TEXT_BASE)
 277
 278 /*
 279  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 280  * older x-loader implementations. And move the BSS area so that it
 281  * doesn't overlap with TEXT_BASE.
 282  */
 283 #define CONFIG_SYS_TEXT_BASE            0x80008000
 284 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 285 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 286
 287 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 288 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 289
 290 #endif /* __CONFIG_H */