include/configs/tao3530.h

   1 /*
   2  * Configuration settings for the TechNexion TAO-3530 SOM
   3  * equipped on Thunder baseboard.
   4  *
   5  * Edward Lin <linuxfae@technexion.com>
   6  * Tapani Utriainen <linuxfae@technexion.com>
   7  *
   8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_H
  14 #define __CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_ARMV7                    /* This is an ARM V7 CPU core */
  20 #define CONFIG_OMAP                     /* in a TI OMAP core */
  21 #define CONFIG_OMAP34XX                 /* which is a 34XX */
  22
  23 #define CONFIG_OMAP_GPIO
  24 #define CONFIG_OMAP_COMMON
  25 #define CONFIG_SYS_GENERIC_BOARD
  26
  27 #define MACH_TYPE_OMAP3_TAO3530         2836
  28
  29 #define CONFIG_SDRC                     /* Has an SDRC controller */
  30
  31 #include <asm/arch/cpu.h>               /* get chip and board defs */
  32 #include <asm/arch/omap3.h>
  33
  34 /*
  35  * Display CPU and Board information
  36  */
  37 #define CONFIG_DISPLAY_CPUINFO
  38 #define CONFIG_DISPLAY_BOARDINFO
  39
  40 /* Clock Defines */
  41 #define V_OSCK                  26000000        /* Clock output from T2 */
  42 #define V_SCLK                  (V_OSCK >> 1)
  43
  44 #define CONFIG_MISC_INIT_R
  45
  46 #define CONFIG_OF_LIBFDT
  47
  48 #define CONFIG_CMDLINE_TAG
  49 #define CONFIG_SETUP_MEMORY_TAGS
  50 #define CONFIG_INITRD_TAG
  51 #define CONFIG_REVISION_TAG
  52
  53 /*
  54  * Size of malloc() pool
  55  */
  56 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)
  57 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
  58
  59 /*
  60  * Hardware drivers
  61  */
  62
  63 /*
  64  * NS16550 Configuration
  65  */
  66 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  67
  68 #define CONFIG_SYS_NS16550
  69 #define CONFIG_SYS_NS16550_SERIAL
  70 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  71 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  72
  73 /*
  74  * select serial console configuration
  75  */
  76 #define CONFIG_CONS_INDEX               3
  77 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  78
  79 /* allow to overwrite serial and ethaddr */
  80 #define CONFIG_ENV_OVERWRITE
  81 #define CONFIG_BAUDRATE                 115200
  82 #define CONFIG_GENERIC_MMC
  83 #define CONFIG_MMC
  84 #define CONFIG_OMAP_HSMMC
  85 #define CONFIG_DOS_PARTITION
  86
  87 /* GPIO banks */
  88 #define CONFIG_OMAP3_GPIO_2             /* GPIO32 ..63  is in GPIO bank 2 */
  89 #define CONFIG_OMAP3_GPIO_3             /* GPIO64 ..95  is in GPIO bank 3 */
  90 #define CONFIG_OMAP3_GPIO_4             /* GPIO96 ..127 is in GPIO bank 4 */
  91 #define CONFIG_OMAP3_GPIO_5             /* GPIO128..159 is in GPIO bank 5 */
  92 #define CONFIG_OMAP3_GPIO_6             /* GPIO160..191 is in GPIO bank 6 */
  93
  94 /* commands to include */
  95 #include <config_cmd_default.h>
  96
  97 #define CONFIG_CMD_CACHE
  98 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
  99 #define CONFIG_CMD_FAT          /* FAT support                  */
 100 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
 101 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 102 #define MTDIDS_DEFAULT                  "nand0=nand"
 103 #define MTDPARTS_DEFAULT                "mtdparts=nand:512k(x-loader),"\
 104                                         "1920k(u-boot),128k(u-boot-env),"\
 105                                         "4m(kernel),-(fs)"
 106
 107 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
 108 #define CONFIG_CMD_MMC          /* MMC support                  */
 109 #define CONFIG_CMD_NAND         /* NAND support                 */
 110 #define CONFIG_CMD_DHCP
 111 #define CONFIG_CMD_PING
 112
 113 #undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 114 #undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 115 #undef CONFIG_CMD_IMI           /* iminfo                       */
 116 #undef CONFIG_CMD_IMLS          /* List all found images        */
 117
 118 #define CONFIG_SYS_NO_FLASH
 119 #define CONFIG_SYS_I2C
 120 #define CONFIG_SYS_I2C_OMAP34XX
 121 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
 122 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
 123 #define CONFIG_I2C_MULTI_BUS
 124
 125 /*
 126  * TWL4030
 127  */
 128 #define CONFIG_TWL4030_POWER
 129 #define CONFIG_TWL4030_LED
 130
 131 /*
 132  * Board NAND Info.
 133  */
 134 #define CONFIG_SYS_NAND_QUIET_TEST
 135 #define CONFIG_NAND_OMAP_GPMC
 136 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 137                                                         /* to access nand */
 138 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 139                                                         /* to access nand at */
 140                                                         /* CS0 */
 141
 142 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 143                                                         /* devices */
 144 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT  16
 145 /* Environment information */
 146 #define CONFIG_BOOTDELAY                3
 147
 148 #define CONFIG_EXTRA_ENV_SETTINGS \
 149         "loadaddr=0x82000000\0" \
 150         "console=ttyO2,115200n8\0" \
 151         "mpurate=600\0" \
 152         "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
 153         "tv_mode=omapfb.mode=tv:ntsc\0" \
 154         "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
 155         "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
 156         "extra_options= \0" \
 157         "mmcdev=0\0" \
 158         "mmcroot=/dev/mmcblk0p2 rw\0" \
 159         "mmcrootfstype=ext3 rootwait\0" \
 160         "nandroot=ubi0:rootfs ubi.mtd=4\0" \
 161         "nandrootfstype=ubifs\0" \
 162         "mmcargs=setenv bootargs console=${console} " \
 163                 "mpurate=${mpurate} " \
 164                 "${video_mode} " \
 165                 "root=${mmcroot} " \
 166                 "rootfstype=${mmcrootfstype} " \
 167                 "${extra_options}\0" \
 168         "nandargs=setenv bootargs console=${console} " \
 169                 "mpurate=${mpurate} " \
 170                 "${video_mode} " \
 171                 "${network_setting} " \
 172                 "root=${nandroot} " \
 173                 "rootfstype=${nandrootfstype} "\
 174                 "${extra_options}\0" \
 175         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 176         "bootscript=echo Running bootscript from mmc ...; " \
 177                 "source ${loadaddr}\0" \
 178         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 179         "mmcboot=echo Booting from mmc ...; " \
 180                 "run mmcargs; " \
 181                 "bootm ${loadaddr}\0" \
 182         "nandboot=echo Booting from nand ...; " \
 183                 "run nandargs; " \
 184                 "nand read ${loadaddr} 280000 400000; " \
 185                 "bootm ${loadaddr}\0" \
 186
 187 #define CONFIG_BOOTCOMMAND \
 188         "if mmc rescan ${mmcdev}; then " \
 189                 "if run loadbootscript; then " \
 190                         "run bootscript; " \
 191                 "else " \
 192                         "if run loaduimage; then " \
 193                                 "run mmcboot; " \
 194                         "else run nandboot; " \
 195                         "fi; " \
 196                 "fi; " \
 197         "else run nandboot; fi"
 198
 199 /*
 200  * Miscellaneous configurable options
 201  */
 202 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 203 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 204 #define CONFIG_SYS_PROMPT               "TAO-3530 # "
 205 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 206
 207 /* turn on command-line edit/hist/auto */
 208 #define CONFIG_CMDLINE_EDITING
 209 #define CONFIG_COMMAND_HISTORY
 210 #define CONFIG_AUTO_COMPLETE
 211
 212 /* Print Buffer Size */
 213 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 214                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 215 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 216 /* Boot Argument Buffer Size */
 217 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 218
 219 #define CONFIG_SYS_ALT_MEMTEST          1
 220 #define CONFIG_SYS_MEMTEST_START        (0x82000000)            /* memtest */
 221                                                                 /* defaults */
 222 #define CONFIG_SYS_MEMTEST_END          (0x83FFFFFF)            /* 64MB */
 223 #define CONFIG_SYS_MEMTEST_SCRATCH      (0x81000000)    /* dummy address */
 224
 225 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 226                                                         /* load address */
 227 #define CONFIG_SYS_TEXT_BASE            0x80008000
 228
 229 /*
 230  * OMAP3 has 12 GP timers, they can be driven by the system clock
 231  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 232  * This rate is divided by a local divisor.
 233  */
 234 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 235 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 236
 237 /*
 238  * Stack sizes
 239  *
 240  * The stack sizes are set up in start.S using the settings below
 241  */
 242 #define CONFIG_STACKSIZE        (128 << 10)     /* regular stack 128 KiB */
 243
 244 /*
 245  * Physical Memory Map
 246  */
 247 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 248 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 249 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
 250 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 251
 252 /*
 253  * FLASH and environment organization
 254  */
 255
 256 /* **** PISMO SUPPORT *** */
 257 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 258 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
 259
 260 /* Monitor at start of flash */
 261 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 262 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 263
 264 #define CONFIG_ENV_IS_IN_NAND           1
 265 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 266 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 267
 268 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)
 269 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 270 #define CONFIG_ENV_ADDR                 CONFIG_ENV_OFFSET
 271
 272 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 273 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 274 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 275 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
 276                                          CONFIG_SYS_INIT_RAM_SIZE - \
 277                                          GENERATED_GBL_DATA_SIZE)
 278
 279 #define CONFIG_OMAP3_SPI
 280
 281 /*
 282  * USB
 283  *
 284  * Currently only EHCI is enabled, the MUSB OTG controller
 285  * is not enabled.
 286  */
 287
 288 /* USB EHCI */
 289 #define CONFIG_CMD_USB
 290 #define CONFIG_USB_EHCI
 291 #define CONFIG_USB_EHCI_OMAP
 292 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        162
 293
 294 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 295 #define CONFIG_USB_HOST_ETHER
 296 #define CONFIG_USB_ETHER_SMSC95XX
 297
 298 #define CONFIG_USB_ETHER
 299 #define CONFIG_USB_ETHER_RNDIS
 300 #define CONFIG_USB_STORAGE
 301 #define CONGIG_CMD_STORAGE
 302
 303 /* Defines for SPL */
 304 #define CONFIG_SPL
 305 #define CONFIG_SPL_FRAMEWORK
 306 #define CONFIG_SPL_NAND_SIMPLE
 307
 308 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
 309 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
 310 #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
 311 #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
 312
 313 #define CONFIG_SPL_BOARD_INIT
 314 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 315 #define CONFIG_SPL_LIBDISK_SUPPORT
 316 #define CONFIG_SPL_I2C_SUPPORT
 317 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 318 #define CONFIG_SPL_MMC_SUPPORT
 319 #define CONFIG_SPL_FAT_SUPPORT
 320 #define CONFIG_SPL_SERIAL_SUPPORT
 321 #define CONFIG_SPL_NAND_SUPPORT
 322 #define CONFIG_SPL_NAND_BASE
 323 #define CONFIG_SPL_NAND_DRIVERS
 324 #define CONFIG_SPL_NAND_ECC
 325 #define CONFIG_SPL_GPIO_SUPPORT
 326 #define CONFIG_SPL_POWER_SUPPORT
 327 #define CONFIG_SPL_OMAP3_ID_NAND
 328 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 329
 330 /* NAND boot config */
 331 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 332 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 333 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 334 #define CONFIG_SYS_NAND_OOBSIZE         64
 335 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 336 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 337 /*
 338  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 339  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 340  */
 341 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 342                                          10, 11, 12, 13 }
 343 #define CONFIG_SYS_NAND_ECCSIZE         512
 344 #define CONFIG_SYS_NAND_ECCBYTES        3
 345 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 346
 347 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 348 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 349
 350 #define CONFIG_SPL_TEXT_BASE            0x40200800
 351 #define CONFIG_SPL_MAX_SIZE             (54 * 1024)     /* 8 KB for stack */
 352 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
 353
 354 /*
 355  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 356  * older x-loader implementations. And move the BSS area so that it
 357  * doesn't overlap with TEXT_BASE.
 358  */
 359 #define CONFIG_SYS_TEXT_BASE            0x80008000
 360 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 361 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 362
 363 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 364 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 365
 366 #endif /* __CONFIG_H */