include/configs/taurus.h

   1 /*
   2  * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
   3  * (C) Copyright 2013 Siemens AG
   4  *
   5  * Based on:
   6  * U-Boot file: include/configs/at91sam9260ek.h
   7  *
   8  * (C) Copyright 2007-2008
   9  * Stelian Pop <stelian@popies.net>
  10  * Lead Tech Design <www.leadtechdesign.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /*
  19  * SoC must be defined first, before hardware.h is included.
  20  * In this case SoC is defined in boards.cfg.
  21  */
  22 #include <asm/hardware.h>
  23 #include <linux/sizes.h>
  24
  25 #if defined(CONFIG_SPL_BUILD)
  26 #define CONFIG_SYS_ICACHE_OFF
  27 #define CONFIG_SYS_DCACHE_OFF
  28 #endif
  29 /*
  30  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  31  * adapting the initial boot program.
  32  * Since the linker has to swallow that define, we must use a pure
  33  * hex number here!
  34  */
  35
  36 /* ARM asynchronous clock */
  37 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock xtal */
  38 #define CONFIG_SYS_AT91_MAIN_CLOCK      18432000        /* main clock xtal */
  39
  40 /* Misc CPU related */
  41 #define CONFIG_ARCH_CPU_INIT
  42 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  43 #define CONFIG_SETUP_MEMORY_TAGS
  44 #define CONFIG_INITRD_TAG
  45 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
  46
  47 /* general purpose I/O */
  48 #define CONFIG_ATMEL_LEGACY             /* required until (g)pio is fixed */
  49 #define CONFIG_AT91_GPIO
  50 #define CONFIG_AT91_GPIO_PULLUP 1       /* keep pullups on peripheral pins */
  51
  52 /* serial console */
  53 #define CONFIG_ATMEL_USART
  54 #define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  55 #define CONFIG_USART_ID                 ATMEL_ID_SYS
  56
  57
  58 /*
  59  * SDRAM: 1 bank, min 32, max 128 MB
  60  * Initialized before u-boot gets started.
  61  */
  62 #define CONFIG_NR_DRAM_BANKS            1
  63 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS1
  64 #define CONFIG_SYS_SDRAM_SIZE           (128 * SZ_1M)
  65
  66 /*
  67  * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
  68  * leaving the correct space for initial global data structure above
  69  * that address while providing maximum stack area below.
  70  */
  71 #define CONFIG_SYS_INIT_SP_ADDR \
  72         (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
  73
  74 /* NAND flash */
  75 #ifdef CONFIG_CMD_NAND
  76 #define CONFIG_NAND_ATMEL
  77 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  78 #define CONFIG_SYS_NAND_BASE            ATMEL_BASE_CS3
  79 #define CONFIG_SYS_NAND_DBW_8
  80 #define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
  81 #define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
  82 #define CONFIG_SYS_NAND_ENABLE_PIN      AT91_PIN_PC14
  83 #define CONFIG_SYS_NAND_READY_PIN       AT91_PIN_PC13
  84 #endif
  85
  86 /* Ethernet */
  87 #define CONFIG_MACB
  88 #define CONFIG_RMII
  89 #define CONFIG_AT91_WANTS_COMMON_PHY
  90
  91 #define CONFIG_AT91SAM9_WATCHDOG
  92 #define CONFIG_AT91_HW_WDT_TIMEOUT      15
  93 #if !defined(CONFIG_SPL_BUILD)
  94 /* Enable the watchdog */
  95 #define CONFIG_HW_WATCHDOG
  96 #endif
  97
  98 /* USB */
  99 #if defined(CONFIG_BOARD_TAURUS)
 100 #define CONFIG_USB_ATMEL
 101 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 102 #define CONFIG_USB_OHCI_NEW
 103 #define CONFIG_SYS_USB_OHCI_CPU_INIT
 104 #define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00500000
 105 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91sam9260"
 106 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 107
 108 /* USB DFU support */
 109 #define CONFIG_MTD_DEVICE
 110 #define CONFIG_MTD_PARTITIONS
 111
 112 #define CONFIG_USB_GADGET_AT91
 113
 114 /* DFU class support */
 115 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (SZ_1M)
 116 #define DFU_MANIFEST_POLL_TIMEOUT       25000
 117 #endif
 118
 119 /* SPI EEPROM */
 120 #define CONFIG_SPI
 121 #define CONFIG_ATMEL_SPI
 122 #define TAURUS_SPI_MASK (1 << 4)
 123 #define TAURUS_SPI_CS_PIN       AT91_PIN_PA3
 124
 125 #if defined(CONFIG_SPL_BUILD)
 126 /* SPL related */
 127 #define CONFIG_SPL_SPI_LOAD
 128 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x20000
 129
 130 #define CONFIG_SF_DEFAULT_BUS 0
 131 #define CONFIG_SF_DEFAULT_SPEED 1000000
 132 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
 133 #endif
 134
 135 /* load address */
 136 #define CONFIG_SYS_LOAD_ADDR                    0x22000000
 137
 138 /* bootstrap in spi flash , u-boot + env + linux in nandflash */
 139 #define CONFIG_ENV_OFFSET               0x100000
 140 #define CONFIG_ENV_OFFSET_REDUND        0x180000
 141 #define CONFIG_ENV_SIZE         (SZ_128K)       /* 1 sector = 128 kB */
 142 #define CONFIG_BOOTCOMMAND      "nand read 0x22000000 0x200000 0x300000; bootm"
 143
 144 /*
 145  * Size of malloc() pool
 146  */
 147 #define CONFIG_SYS_MALLOC_LEN \
 148         ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000)
 149
 150 /* Defines for SPL */
 151 #define CONFIG_SPL_TEXT_BASE            0x0
 152 #define CONFIG_SPL_MAX_SIZE             (31 * SZ_512)
 153 #define CONFIG_SPL_STACK                (ATMEL_BASE_SRAM1 + SZ_16K)
 154 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
 155                                         CONFIG_SYS_MALLOC_LEN)
 156 #define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
 157
 158 #define CONFIG_SPL_BSS_START_ADDR       CONFIG_SPL_MAX_SIZE
 159 #define CONFIG_SPL_BSS_MAX_SIZE         (3 * SZ_512)
 160
 161 #define CONFIG_SYS_NAND_ENABLE_PIN_SPL  (2*32 + 14)
 162 #define CONFIG_SYS_USE_NANDFLASH        1
 163 #define CONFIG_SPL_NAND_DRIVERS
 164 #define CONFIG_SPL_NAND_BASE
 165 #define CONFIG_SPL_NAND_ECC
 166 #define CONFIG_SPL_NAND_RAW_ONLY
 167 #define CONFIG_SPL_NAND_SOFTECC
 168 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
 169 #define CONFIG_SYS_NAND_U_BOOT_SIZE     SZ_512K
 170 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 171 #define CONFIG_SYS_NAND_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
 172 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 173
 174 #define CONFIG_SYS_NAND_SIZE            (256 * SZ_1M)
 175 #define CONFIG_SYS_NAND_PAGE_SIZE       SZ_2K
 176 #define CONFIG_SYS_NAND_BLOCK_SIZE      (SZ_128K)
 177 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
 178                                          CONFIG_SYS_NAND_PAGE_SIZE)
 179 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 180 #define CONFIG_SYS_NAND_ECCSIZE         256
 181 #define CONFIG_SYS_NAND_ECCBYTES        3
 182 #define CONFIG_SYS_NAND_OOBSIZE         64
 183 #define CONFIG_SYS_NAND_ECCPOS          { 40, 41, 42, 43, 44, 45, 46, 47, \
 184                                           48, 49, 50, 51, 52, 53, 54, 55, \
 185                                           56, 57, 58, 59, 60, 61, 62, 63, }
 186
 187 #define CONFIG_SPL_ATMEL_SIZE
 188 #define CONFIG_SYS_MASTER_CLOCK         132096000
 189 #define AT91_PLL_LOCK_TIMEOUT           1000000
 190 #define CONFIG_SYS_AT91_PLLA            0x202A3F01
 191 #define CONFIG_SYS_MCKR                 0x1300
 192 #define CONFIG_SYS_MCKR_CSS             (0x02 | CONFIG_SYS_MCKR)
 193 #define CONFIG_SYS_AT91_PLLB            0x10193F05
 194
 195 #endif