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1 /*
2 * Copyright (C) 2014 Soeren Moch <smoch@web.de>
3 *
4 * Configuration settings for the TBS2910 MatrixARM board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __TBS2910_CONFIG_H
10 #define __TBS2910_CONFIG_H
11
12 #include "mx6_common.h"
13
14 /* General configuration */
15 #define CONFIG_SYS_THUMB_BUILD
16
17 #define CONFIG_MACH_TYPE 3980
18
19 #define CONFIG_BOARD_EARLY_INIT_F
20
21 #define CONFIG_SYS_HZ 1000
22
23 #define CONFIG_IMX_THERMAL
24
25 /* Physical Memory Map */
26 #define CONFIG_NR_DRAM_BANKS 1
27 #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
28
29 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
30 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
31 #define CONFIG_SYS_INIT_SP_OFFSET \
32 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
33 #define CONFIG_SYS_INIT_SP_ADDR \
34 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
35
36 #define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
37
38 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
39 #define CONFIG_SYS_MEMTEST_END \
40 (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
41
42 #define CONFIG_SYS_BOOTMAPSZ 0x10000000
43
44 /* Serial console */
45 #define CONFIG_MXC_UART
46 #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
47 #define CONFIG_BAUDRATE 115200
48
49 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
50 #define CONFIG_CONSOLE_MUX
51 #define CONFIG_CONS_INDEX 1
52
53 /* *** Command definition *** */
54 #define CONFIG_CMD_BMODE
55 #define CONFIG_CMD_PART
56
57 /* Filesystems / image support */
58 #define CONFIG_EFI_PARTITION
59 #define CONFIG_PARTITION_UUIDS
60
61 /* MMC */
62 #define CONFIG_SYS_FSL_USDHC_NUM 3
63 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
64 #define CONFIG_SUPPORT_EMMC_BOOT
65
66 /* Ethernet */
67 #define CONFIG_FEC_MXC
68 #define CONFIG_FEC_MXC
69 #define CONFIG_MII
70 #define IMX_FEC_BASE ENET_BASE_ADDR
71 #define CONFIG_FEC_XCV_TYPE RGMII
72 #define CONFIG_ETHPRIME "FEC"
73 #define CONFIG_FEC_MXC_PHYADDR 4
74 #define CONFIG_PHYLIB
75 #define CONFIG_PHY_ATHEROS
76
77 /* Framebuffer */
78 #ifdef CONFIG_VIDEO
79 #define CONFIG_VIDEO_IPUV3
80 #define CONFIG_IPUV3_CLK 260000000
81 #define CONFIG_CFB_CONSOLE
82 #define CONFIG_CFB_CONSOLE_ANSI
83 #define CONFIG_VIDEO_SW_CURSOR
84 #define CONFIG_VGA_AS_SINGLE_DEVICE
85 #define CONFIG_VIDEO_BMP_RLE8
86 #define CONFIG_IMX_HDMI
87 #define CONFIG_IMX_VIDEO_SKIP
88 #define CONFIG_CMD_HDMIDETECT
89 #endif
90
91 /* PCI */
92 #define CONFIG_CMD_PCI
93 #ifdef CONFIG_CMD_PCI
94 #define CONFIG_PCI
95 #define CONFIG_PCI_PNP
96 #define CONFIG_PCI_SCAN_SHOW
97 #define CONFIG_PCIE_IMX
98 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
99 #endif
100
101 /* SATA */
102 #define CONFIG_CMD_SATA
103 #ifdef CONFIG_CMD_SATA
104 #define CONFIG_DWC_AHSATA
105 #define CONFIG_SYS_SATA_MAX_DEVICE 1
106 #define CONFIG_DWC_AHSATA_PORT_ID 0
107 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
108 #define CONFIG_LBA48
109 #define CONFIG_LIBATA
110 #endif
111
112 /* USB */
113 #ifdef CONFIG_CMD_USB
114 #define CONFIG_USB_EHCI
115 #define CONFIG_USB_EHCI_MX6
116 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
117 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
118 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
119 #ifdef CONFIG_CMD_USB_MASS_STORAGE
120 #define CONFIG_USBD_HS
121 #define CONFIG_USB_FUNCTION_MASS_STORAGE
122 #endif /* CONFIG_CMD_USB_MASS_STORAGE */
123 #define CONFIG_USB_KEYBOARD
124 #ifdef CONFIG_USB_KEYBOARD
125 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
126 #define CONFIG_SYS_STDIO_DEREGISTER
127 #define CONFIG_PREBOOT \
128 "usb start; " \
129 "if hdmidet; then " \
130 "run set_con_hdmi; " \
131 "else " \
132 "run set_con_serial; " \
133 "fi;"
134 #endif /* CONFIG_USB_KEYBOARD */
135 #endif /* CONFIG_CMD_USB */
136
137 /* RTC */
138 #define CONFIG_CMD_DATE
139 #ifdef CONFIG_CMD_DATE
140 #define CONFIG_RTC_DS1307
141 #define CONFIG_SYS_RTC_BUS_NUM 2
142 #endif
143
144 /* I2C */
145 #ifdef CONFIG_CMD_I2C
146 #define CONFIG_SYS_I2C
147 #define CONFIG_SYS_I2C_MXC
148 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
149 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
150 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
151 #define CONFIG_SYS_I2C_SPEED 100000
152 #define CONFIG_I2C_EDID
153 #endif
154
155 /* Environment organization */
156 #define CONFIG_ENV_IS_IN_MMC
157 #define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
158 #define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
159 #define CONFIG_ENV_SIZE (8 * 1024)
160 #define CONFIG_ENV_OFFSET (384 * 1024)
161 #define CONFIG_ENV_OVERWRITE
162
163 #define CONFIG_EXTRA_ENV_SETTINGS \
164 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
165 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
166 "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
167 "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
168 "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
169 "${bootargs_mmc3}\0" \
170 "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
171 "rdinit=/sbin/init enable_wait_mode=off\0" \
172 "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
173 "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
174 "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
175 "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
176 "run bootargs_upd; " \
177 "bootm 0x10800000 0x10d00000\0" \
178 "console=ttymxc0\0" \
179 "fan=gpio set 92\0" \
180 "set_con_serial=setenv stdout serial; " \
181 "setenv stderr serial;\0" \
182 "set_con_hdmi=setenv stdout serial,vga; " \
183 "setenv stderr serial,vga;\0" \
184 "stderr=serial,vga;\0" \
185 "stdin=serial,usbkbd;\0" \
186 "stdout=serial,vga;\0"
187
188 #define CONFIG_BOOTCOMMAND \
189 "mmc rescan; " \
190 "if run bootcmd_up1; then " \
191 "run bootcmd_up2; " \
192 "else " \
193 "run bootcmd_mmc; " \
194 "fi"
195
196 #endif /* __TBS2910_CONFIG_H * */