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1 /*
2 * Copyright (C) 2014 Soeren Moch <smoch@web.de>
3 *
4 * Configuration settings for the TBS2910 MatrixARM board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #ifndef __TBS2910_CONFIG_H
10 #define __TBS2910_CONFIG_H
11
12 #include "mx6_common.h"
13
14 /* General configuration */
15 #define CONFIG_SYS_THUMB_BUILD
16
17 #define CONFIG_MACH_TYPE 3980
18
19 #define CONFIG_BOARD_EARLY_INIT_F
20
21 #define CONFIG_SYS_HZ 1000
22
23 #define CONFIG_IMX_THERMAL
24
25 /* Physical Memory Map */
26 #define CONFIG_NR_DRAM_BANKS 1
27 #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
28
29 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
30 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
31 #define CONFIG_SYS_INIT_SP_OFFSET \
32 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
33 #define CONFIG_SYS_INIT_SP_ADDR \
34 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
35
36 #define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
37
38 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
39 #define CONFIG_SYS_MEMTEST_END \
40 (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
41
42 #define CONFIG_SYS_BOOTMAPSZ 0x6C000000
43
44 /* Serial console */
45 #define CONFIG_MXC_UART
46 #define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
47 #define CONFIG_BAUDRATE 115200
48
49 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
50 #define CONFIG_CONSOLE_MUX
51 #define CONFIG_CONS_INDEX 1
52
53 #define CONFIG_PRE_CONSOLE_BUFFER
54 #define CONFIG_PRE_CON_BUF_SZ 4096
55 #define CONFIG_PRE_CON_BUF_ADDR 0x7C000000
56
57 /* *** Command definition *** */
58 #define CONFIG_CMD_BMODE
59
60 /* Filesystems / image support */
61 #define CONFIG_EFI_PARTITION
62
63 /* MMC */
64 #define CONFIG_SYS_FSL_USDHC_NUM 3
65 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
66 #define CONFIG_SUPPORT_EMMC_BOOT
67
68 /* Ethernet */
69 #define CONFIG_FEC_MXC
70 #define CONFIG_FEC_MXC
71 #define CONFIG_MII
72 #define IMX_FEC_BASE ENET_BASE_ADDR
73 #define CONFIG_FEC_XCV_TYPE RGMII
74 #define CONFIG_ETHPRIME "FEC"
75 #define CONFIG_FEC_MXC_PHYADDR 4
76 #define CONFIG_PHYLIB
77 #define CONFIG_PHY_ATHEROS
78
79 /* Framebuffer */
80 #define CONFIG_VIDEO
81 #ifdef CONFIG_VIDEO
82 #define CONFIG_VIDEO_IPUV3
83 #define CONFIG_IPUV3_CLK 260000000
84 #define CONFIG_CFB_CONSOLE
85 #define CONFIG_CFB_CONSOLE_ANSI
86 #define CONFIG_VIDEO_SW_CURSOR
87 #define CONFIG_VGA_AS_SINGLE_DEVICE
88 #define CONFIG_VIDEO_BMP_RLE8
89 #define CONFIG_IMX_HDMI
90 #define CONFIG_IMX_VIDEO_SKIP
91 #define CONFIG_CMD_HDMIDETECT
92 #endif
93
94 /* PCI */
95 #define CONFIG_CMD_PCI
96 #ifdef CONFIG_CMD_PCI
97 #define CONFIG_PCI
98 #define CONFIG_PCI_PNP
99 #define CONFIG_PCI_SCAN_SHOW
100 #define CONFIG_PCIE_IMX
101 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
102 #endif
103
104 /* SATA */
105 #define CONFIG_CMD_SATA
106 #ifdef CONFIG_CMD_SATA
107 #define CONFIG_DWC_AHSATA
108 #define CONFIG_SYS_SATA_MAX_DEVICE 1
109 #define CONFIG_DWC_AHSATA_PORT_ID 0
110 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
111 #define CONFIG_LBA48
112 #define CONFIG_LIBATA
113 #endif
114
115 /* USB */
116 #ifdef CONFIG_CMD_USB
117 #define CONFIG_USB_EHCI
118 #define CONFIG_USB_EHCI_MX6
119 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
120 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
121 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
122 #define CONFIG_USB_STORAGE
123 #ifdef CONFIG_CMD_USB_MASS_STORAGE
124 #define CONFIG_USBD_HS
125 #define CONFIG_USB_FUNCTION_MASS_STORAGE
126 #endif /* CONFIG_CMD_USB_MASS_STORAGE */
127 #define CONFIG_USB_KEYBOARD
128 #ifdef CONFIG_USB_KEYBOARD
129 #define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
130 #define CONFIG_SYS_STDIO_DEREGISTER
131 #define CONFIG_PREBOOT \
132 "usb start; " \
133 "if hdmidet; then " \
134 "run set_con_hdmi; " \
135 "else " \
136 "run set_con_serial; " \
137 "fi;"
138 #endif /* CONFIG_USB_KEYBOARD */
139 #endif /* CONFIG_CMD_USB */
140
141 /* RTC */
142 #define CONFIG_CMD_DATE
143 #ifdef CONFIG_CMD_DATE
144 #define CONFIG_RTC_DS1307
145 #define CONFIG_SYS_RTC_BUS_NUM 2
146 #endif
147
148 /* I2C */
149 #ifdef CONFIG_CMD_I2C
150 #define CONFIG_SYS_I2C
151 #define CONFIG_SYS_I2C_MXC
152 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
153 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
154 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
155 #define CONFIG_SYS_I2C_SPEED 100000
156 #define CONFIG_I2C_EDID
157 #endif
158
159 /* Environment organization */
160 #define CONFIG_ENV_IS_IN_MMC
161 #define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
162 #define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
163 #define CONFIG_ENV_SIZE (8 * 1024)
164 #define CONFIG_ENV_OFFSET (384 * 1024)
165 #define CONFIG_ENV_OVERWRITE
166
167 #define CONFIG_EXTRA_ENV_SETTINGS \
168 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
169 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
170 "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
171 "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
172 "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
173 "${bootargs_mmc3}\0" \
174 "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
175 "rdinit=/sbin/init enable_wait_mode=off\0" \
176 "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
177 "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
178 "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
179 "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
180 "run bootargs_upd; " \
181 "bootm 0x10800000 0x10d00000\0" \
182 "console=ttymxc0\0" \
183 "fan=gpio set 92\0" \
184 "set_con_serial=setenv stdout serial; " \
185 "setenv stderr serial;\0" \
186 "set_con_hdmi=setenv stdout serial,vga; " \
187 "setenv stderr serial,vga;\0" \
188 "stdin=serial,usbkbd;\0"
189
190 #define CONFIG_BOOTCOMMAND \
191 "mmc rescan; " \
192 "if run bootcmd_up1; then " \
193 "run bootcmd_up2; " \
194 "else " \
195 "run bootcmd_mmc; " \
196 "fi"
197
198 #endif /* __TBS2910_CONFIG_H * */