include/configs/tegra30-common.h

   1 /*
   2  *  (C) Copyright 2010-2012
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _TEGRA30_COMMON_H_
   9 #define _TEGRA30_COMMON_H_
  10 #include "tegra-common.h"
  11
  12 /*
  13  * Errata configuration
  14  */
  15 #define CONFIG_ARM_ERRATA_743622
  16 #define CONFIG_ARM_ERRATA_751472
  17
  18 /*
  19  * NS16550 Configuration
  20  */
  21 #define V_NS16550_CLK           408000000       /* 408MHz (pllp_out0) */
  22
  23 /*
  24  * Miscellaneous configurable options
  25  */
  26 #define CONFIG_STACKBASE        0x82800000      /* 40MB */
  27
  28 /*-----------------------------------------------------------------------
  29  * Physical Memory Map
  30  */
  31 #define CONFIG_SYS_TEXT_BASE    0x80110000
  32
  33 /*
  34  * Memory layout for where various images get loaded by boot scripts:
  35  *
  36  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  37  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  38  *
  39  * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  40  *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
  41  *
  42  * kernel_addr_r must be within the first 128M of RAM in order for the
  43  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  44  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  45  *   should not overlap that area, or the kernel will have to copy itself
  46  *   somewhere else before decompression. Similarly, the address of any other
  47  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
  48  *   this up to 16M allows for a sizable kernel to be decompressed below the
  49  *   compressed load address.
  50  *
  51  * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  52  *   the compressed kernel to be up to 16M too.
  53  *
  54  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  55  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  56  */
  57 #define CONFIG_LOADADDR 0x81000000
  58 #define MEM_LAYOUT_ENV_SETTINGS \
  59         "scriptaddr=0x90000000\0" \
  60         "pxefile_addr_r=0x90100000\0" \
  61         "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  62         "fdt_addr_r=0x82000000\0" \
  63         "ramdisk_addr_r=0x82100000\0"
  64
  65 /* Defines for SPL */
  66 #define CONFIG_SPL_TEXT_BASE            0x80108000
  67 #define CONFIG_SYS_SPL_MALLOC_START     0x80090000
  68 #define CONFIG_SPL_STACK                0x800ffffc
  69
  70 /* For USB EHCI controller */
  71 #define CONFIG_EHCI_IS_TDI
  72 #define CONFIG_USB_EHCI_TXFIFO_THRESH   0x10
  73 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
  74
  75 #endif /* _TEGRA30_COMMON_H_ */