include/configs/theadorable.h

   1 /*
   2  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_THEADORABLE_H
   8 #define _CONFIG_THEADORABLE_H
   9
  10 /*
  11  * High Level Configuration Options (easy to change)
  12  */
  13 #define CONFIG_DISPLAY_BOARDINFO_LATE
  14
  15 /*
  16  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  17  * for DDR ECC byte filling in the SPL before loading the main
  18  * U-Boot into it.
  19  */
  20 #define CONFIG_SYS_TEXT_BASE    0x00800000
  21 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  22
  23 /*
  24  * Commands configuration
  25  */
  26 #define CONFIG_CMD_BOOTZ
  27 #define CONFIG_CMD_CACHE
  28 #define CONFIG_CMD_ENV
  29 #define CONFIG_CMD_EXT2
  30 #define CONFIG_CMD_EXT4
  31 #define CONFIG_CMD_FAT
  32 #define CONFIG_CMD_FS_GENERIC
  33 #define CONFIG_CMD_I2C
  34 #define CONFIG_CMD_SATA
  35 #define CONFIG_CMD_TIME
  36
  37 /*
  38  * The debugging version enables USB support via defconfig.
  39  * This version should also enable all other non-production
  40  * interfaces / features.
  41  */
  42 #ifdef CONFIG_USB
  43 #define CONFIG_CMD_DHCP
  44 #define CONFIG_CMD_PCI
  45 #define CONFIG_CMD_PING
  46 #define CONFIG_CMD_SPI
  47 #define CONFIG_CMD_TFTPPUT
  48 #endif
  49
  50 /* I2C */
  51 #define CONFIG_SYS_I2C
  52 #define CONFIG_SYS_I2C_MVTWSI
  53 #define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  54 #define CONFIG_SYS_I2C_SLAVE            0x0
  55 #define CONFIG_SYS_I2C_SPEED            100000
  56
  57 /* USB/EHCI configuration */
  58 #define CONFIG_EHCI_IS_TDI
  59 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  60
  61 #define CONFIG_SYS_NO_FLASH             /* Declare no flash (NOR/SPI) */
  62
  63 /* SPI NOR flash default params, used by sf commands */
  64 #define CONFIG_SF_DEFAULT_SPEED         27777777 /* for fast SPL booting */
  65 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
  66
  67 /* Environment in SPI NOR flash */
  68 #define CONFIG_ENV_IS_IN_SPI_FLASH
  69 #define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  70 #define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  71 #define CONFIG_ENV_SECT_SIZE            (256 << 10) /* 256KiB sectors */
  72 #define CONFIG_ENV_OVERWRITE
  73
  74 #define CONFIG_PHY_MARVELL              /* there is a marvell phy */
  75 #define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  76
  77 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup */
  78 #define CONFIG_SYS_ALT_MEMTEST
  79 #define CONFIG_PREBOOT
  80
  81 #define CONFIG_SYS_HUSH_PARSER                  /* Use the HUSH parser  */
  82 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
  83
  84 /* Keep device tree and initrd in lower memory so the kernel can access them */
  85 #define CONFIG_EXTRA_ENV_SETTINGS       \
  86         "fdt_high=0x10000000\0"         \
  87         "initrd_high=0x10000000\0"
  88
  89 /* SATA support */
  90 #define CONFIG_SYS_SATA_MAX_DEVICE      1
  91 #define CONFIG_SATA_MV
  92 #define CONFIG_LIBATA
  93 #define CONFIG_LBA48
  94 #define CONFIG_EFI_PARTITION
  95 #define CONFIG_DOS_PARTITION
  96
  97 /* Additional FS support/configuration */
  98 #define CONFIG_SUPPORT_VFAT
  99
 100 /* PCIe support */
 101 #ifdef CONFIG_CMD_PCI
 102 #ifndef CONFIG_SPL_BUILD
 103 #define CONFIG_PCI
 104 #define CONFIG_PCI_MVEBU
 105 #define CONFIG_PCI_PNP
 106 #endif
 107 #endif
 108
 109 /* Enable LCD and reserve 512KB from top of memory*/
 110 #define CONFIG_SYS_MEM_TOP_HIDE         0x80000
 111
 112 #define CONFIG_VIDEO
 113 #define CONFIG_CFB_CONSOLE
 114 #define CONFIG_VGA_AS_SINGLE_DEVICE
 115 #define CONFIG_CMD_BMP
 116
 117 /* FPGA programming support */
 118 #define CONFIG_FPGA
 119 #define CONFIG_FPGA_ALTERA
 120 #define CONFIG_FPGA_STRATIX_V
 121
 122 /*
 123  * mv-common.h should be defined after CMD configs since it used them
 124  * to enable certain macros
 125  */
 126 #include "mv-common.h"
 127
 128 /*
 129  * Memory layout while starting into the bin_hdr via the
 130  * BootROM:
 131  *
 132  * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
 133  * 0x4000.4030                  bin_hdr start address
 134  * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
 135  * 0x4007.fffc                  BootROM stack top
 136  *
 137  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 138  * L2 cache thus cannot be used.
 139  */
 140
 141 /* SPL */
 142 /* Defines for SPL */
 143 #define CONFIG_SPL_FRAMEWORK
 144 #define CONFIG_SPL_TEXT_BASE            0x40004030
 145 #define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
 146
 147 #define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
 148 #define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
 149
 150 #ifdef CONFIG_SPL_BUILD
 151 #define CONFIG_SYS_MALLOC_SIMPLE
 152 #endif
 153
 154 #define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
 155 #define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
 156
 157 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 158 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 159 #define CONFIG_SPL_SERIAL_SUPPORT
 160 #define CONFIG_SPL_I2C_SUPPORT
 161
 162 /* SPL related SPI defines */
 163 #define CONFIG_SPL_SPI_SUPPORT
 164 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 165 #define CONFIG_SPL_SPI_LOAD
 166 #define CONFIG_SPL_SPI_BUS              0
 167 #define CONFIG_SPL_SPI_CS               0
 168 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x1a000
 169 #define CONFIG_SYS_U_BOOT_OFFS          CONFIG_SYS_SPI_U_BOOT_OFFS
 170
 171 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 172 #define CONFIG_DDR_FIXED_SIZE           (2 << 20)       /* 2GiB */
 173
 174 #endif /* _CONFIG_THEADORABLE_H */