include/configs/ti816x_evm.h

   1 /*
   2  * ti816x_evm.h
   3  *
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Antoine Tenart, <atenart@adeneo-embedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __CONFIG_TI816X_EVM_H
  11 #define __CONFIG_TI816X_EVM_H
  12
  13 #define CONFIG_TI81XX
  14 #define CONFIG_TI816X
  15
  16 #define CONFIG_ARCH_CPU_INIT
  17
  18 #include <asm/arch/omap.h>
  19
  20 #define CONFIG_ENV_SIZE                 0x2000
  21 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (32 * 1024))
  22 #define CONFIG_SYS_LONGHELP             /* undef save memory */
  23 #define CONFIG_MACH_TYPE                MACH_TYPE_TI8168EVM
  24
  25 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  26 #define CONFIG_SETUP_MEMORY_TAGS
  27 #define CONFIG_INITRD_TAG               /* required for ramdisk support */
  28
  29 #define CONFIG_EXTRA_ENV_SETTINGS       \
  30         "loadaddr=0x81000000\0"         \
  31
  32 #define CONFIG_BOOTCOMMAND                      \
  33         "mmc rescan;"                           \
  34         "fatload mmc 0 ${loadaddr} uImage;"     \
  35         "bootm ${loadaddr}"                     \
  36
  37 #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
  38
  39 /* Clock Defines */
  40 #define V_OSCK          24000000    /* Clock output from T2 */
  41 #define V_SCLK          (V_OSCK >> 1)
  42
  43 #define CONFIG_SYS_MAXARGS      32
  44 #define CONFIG_SYS_CBSIZE       512 /* console I/O buffer size */
  45 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
  46                 + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
  47 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE /* boot arg buffer size */
  48
  49 #define CONFIG_SYS_LOAD_ADDR            0x81000000 /* Default load address */
  50
  51 #define CONFIG_CMD_ASKENV
  52
  53 #define CONFIG_NR_DRAM_BANKS    2               /* we have 2 banks of DRAM */
  54 #define PHYS_DRAM_1             0x80000000      /* DRAM Bank #1 */
  55 #define PHYS_DRAM_1_SIZE        0x40000000      /* 1 GB */
  56 #define PHYS_DRAM_2             0xC0000000      /* DRAM Bank #2 */
  57 #define PHYS_DRAM_2_SIZE        0x40000000      /* 1 GB */
  58
  59 #define CONFIG_MAX_RAM_BANK_SIZE        (2048 << 20)    /* 2048MB */
  60 #define CONFIG_SYS_SDRAM_BASE           PHYS_DRAM_1
  61 #define CONFIG_SYS_INIT_SP_ADDR         (NON_SECURE_SRAM_END - \
  62                 GENERATED_GBL_DATA_SIZE)
  63
  64 /**
  65  * Platform/Board specific defs
  66  */
  67 #define CONFIG_SYS_CLK_FREQ     27000000
  68 #define CONFIG_SYS_TIMERBASE    0x4802E000
  69 #define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */
  70
  71 /*
  72  * NS16550 Configuration
  73  */
  74 #define CONFIG_SYS_NS16550_SERIAL
  75 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  76 #define CONFIG_SYS_NS16550_CLK      (48000000)
  77 #define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */
  78
  79 /* allow overwriting serial config and ethaddr */
  80 #define CONFIG_ENV_OVERWRITE
  81
  82 #define CONFIG_SERIAL1
  83 #define CONFIG_SERIAL2
  84 #define CONFIG_SERIAL3
  85 #define CONFIG_CONS_INDEX       1
  86
  87 /*
  88  * GPMC NAND block.  We support 1 device and the physical address to
  89  * access CS0 at is 0x8000000.
  90  */
  91 #define CONFIG_SYS_NAND_BASE            0x8000000
  92 #define CONFIG_SYS_MAX_NAND_DEVICE      1
  93
  94 /* NAND: SPL related configs */
  95 #define CONFIG_SPL_NAND_BASE
  96 #define CONFIG_SPL_NAND_DRIVERS
  97 #define CONFIG_SPL_NAND_ECC
  98 #define CONFIG_SPL_NAND_AM33XX_BCH
  99 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 100
 101 /* NAND: device related configs */
 102 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 103 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 104 #define CONFIG_SYS_NAND_PAGE_COUNT      (CONFIG_SYS_NAND_BLOCK_SIZE / \
 105                                          CONFIG_SYS_NAND_PAGE_SIZE)
 106 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 107 #define CONFIG_SYS_NAND_OOBSIZE         64
 108 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 109 /* NAND: driver related configs */
 110 #define CONFIG_NAND_OMAP_GPMC
 111 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
 112 #define CONFIG_NAND_OMAP_ELM
 113 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 114 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
 115                                          10, 11, 12, 13, 14, 15, 16, 17, \
 116                                          18, 19, 20, 21, 22, 23, 24, 25, \
 117                                          26, 27, 28, 29, 30, 31, 32, 33, \
 118                                          34, 35, 36, 37, 38, 39, 40, 41, \
 119                                          42, 43, 44, 45, 46, 47, 48, 49, \
 120                                          50, 51, 52, 53, 54, 55, 56, 57, }
 121
 122 #define CONFIG_SYS_NAND_ECCSIZE         512
 123 #define CONFIG_SYS_NAND_ECCBYTES        14
 124 #define CONFIG_SYS_NAND_ONFI_DETECTION
 125 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW
 126 #define MTDIDS_DEFAULT                  "nand0=nand.0"
 127 #define MTDPARTS_DEFAULT                "mtdparts=nand.0:" \
 128                                         "128k(NAND.SPL)," \
 129                                         "128k(NAND.SPL.backup1)," \
 130                                         "128k(NAND.SPL.backup2)," \
 131                                         "128k(NAND.SPL.backup3)," \
 132                                         "256k(NAND.u-boot-spl-os)," \
 133                                         "1m(NAND.u-boot)," \
 134                                         "128k(NAND.u-boot-env)," \
 135                                         "128k(NAND.u-boot-env.backup1)," \
 136                                         "8m(NAND.kernel)," \
 137                                         "-(NAND.file-system)"
 138 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x000c0000
 139 #define CONFIG_ENV_IS_IN_NAND
 140 #define CONFIG_ENV_OFFSET               0x001c0000
 141 #define CONFIG_ENV_OFFSET_REDUND        0x001e0000
 142 #define CONFIG_SYS_ENV_SECT_SIZE        CONFIG_SYS_NAND_BLOCK_SIZE
 143
 144 /* SPL */
 145 /* Defines for SPL */
 146 #define CONFIG_SPL_NAND_AM33XX_BCH      /* ELM support */
 147 #define CONFIG_SPL_FRAMEWORK
 148 #define CONFIG_SPL_TEXT_BASE    0x40400000
 149 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 150                                          CONFIG_SPL_TEXT_BASE)
 151
 152 #define CONFIG_SPL_BSS_START_ADDR   0x80000000
 153 #define CONFIG_SPL_BSS_MAX_SIZE     0x80000     /* 512 KB */
 154
 155 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 156 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
 157
 158 #define CONFIG_SYS_SPI_U_BOOT_OFFS  0x20000
 159 #define CONFIG_SYS_SPI_U_BOOT_SIZE  0x40000
 160 #define CONFIG_SPL_LDSCRIPT     "arch/arm/mach-omap2/u-boot-spl.lds"
 161
 162 #define CONFIG_SYS_TEXT_BASE        0x80800000
 163 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
 164 #define CONFIG_SYS_SPL_MALLOC_SIZE  0x100000
 165
 166 /* Since SPL did pll and ddr initialization for us,
 167  * we don't need to do it twice.
 168  */
 169 #ifndef CONFIG_SPL_BUILD
 170 #define CONFIG_SKIP_LOWLEVEL_INIT
 171 #endif
 172
 173 #endif