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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/tricorder.h
2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
11 * Configuration settings for the Tricorder board.
13 * SPDX-License-Identifier: GPL-2.0+
19 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
21 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
22 * 64 bytes before this address should be set aside for u-boot.img's
23 * header. That is 0x800FFFC0--0x80100000 should not be used for any
26 #define CONFIG_SYS_TEXT_BASE 0x80100000
28 #define CONFIG_SDRC /* The chip has SDRC controller */
30 #include <asm/arch/cpu.h> /* get chip and board defs */
31 #include <asm/arch/omap.h>
34 #define V_OSCK 26000000 /* Clock output from T2 */
35 #define V_SCLK (V_OSCK >> 1)
37 #define CONFIG_MISC_INIT_R
39 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
40 #define CONFIG_SETUP_MEMORY_TAGS
41 #define CONFIG_INITRD_TAG
42 #define CONFIG_REVISION_TAG
44 /* Size of malloc() pool */
45 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
47 /* Hardware drivers */
49 /* NS16550 Configuration */
50 #define CONFIG_SYS_NS16550_SERIAL
51 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
52 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
54 /* select serial console configuration */
55 #define CONFIG_CONS_INDEX 3
56 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
57 #define CONFIG_SERIAL3 3
58 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
62 #define CONFIG_SYS_I2C
63 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
64 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
65 #define CONFIG_SYS_I2C_OMAP34XX
69 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
70 #define CONFIG_SYS_EEPROM_BUS_NUM 1
73 #define CONFIG_TWL4030_LED
76 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
77 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
78 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
81 "384k(u-boot-env1)," \
83 "384k(u-boot-env2)," \
88 #define CONFIG_NAND_OMAP_GPMC
89 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
91 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
92 /* to access nand at */
94 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
97 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
98 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
100 /* commands to include */
101 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
102 #define CONFIG_CMD_NAND /* NAND support */
103 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
104 #define CONFIG_CMD_UBIFS /* UBIFS commands */
105 #define CONFIG_LZO /* LZO is needed for UBIFS */
107 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
110 #define CONFIG_RBTREE
111 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
112 #define CONFIG_MTD_PARTITIONS
114 /* Environment information (this is the common part) */
117 /* hang() the board on panic() */
118 #define CONFIG_PANIC_HANG
120 /* environment placement (for NAND), is different for FLASHCARD but does not
122 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
123 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
124 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
125 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
127 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
128 * value can not be used here! */
129 #define CONFIG_LOADADDR 0x82000000
131 #define CONFIG_COMMON_ENV_SETTINGS \
132 "console=ttyO2,115200n8\0" \
135 "defaultdisplay=lcd\0" \
136 "kernelopts=mtdoops.mtddev=3\0" \
137 "mtdparts=" MTDPARTS_DEFAULT "\0" \
138 "mtdids=" MTDIDS_DEFAULT "\0" \
140 "setenv bootargs console=${console} " \
143 "vt.global_cursor_default=0 " \
145 "omapdss.def_disp=${defaultdisplay}\0"
147 #define CONFIG_BOOTCOMMAND "run autoboot"
149 /* specific environment settings for different use cases
150 * FLASHCARD: used to run a rdimage from sdcard to program the device
151 * 'NORMAL': used to boot kernel from sdcard, nand, ...
153 * The main aim for the FLASHCARD skin is to have an embedded environment
154 * which will not be influenced by any data already on the device.
156 #ifdef CONFIG_FLASHCARD
158 #define CONFIG_ENV_IS_NOWHERE
160 /* the rdaddr is 16 MiB before the loadaddr */
161 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
163 #define CONFIG_EXTRA_ENV_SETTINGS \
164 CONFIG_COMMON_ENV_SETTINGS \
168 "setenv bootargs ${bootargs} " \
169 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
170 "rdinit=/sbin/init; " \
171 "mmc dev ${mmcdev}; mmc rescan; " \
172 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
173 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
174 "bootm ${loadaddr} ${rdaddr}\0"
176 #else /* CONFIG_FLASHCARD */
178 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
180 #define CONFIG_ENV_IS_IN_NAND
182 #define CONFIG_EXTRA_ENV_SETTINGS \
183 CONFIG_COMMON_ENV_SETTINGS \
186 "setenv bootargs ${bootargs} " \
187 "root=/dev/mmcblk0p2 " \
192 "setenv bootargs ${bootargs} " \
195 "rootfstype=ubifs " \
197 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
198 "bootscript=echo Running bootscript from mmc ...; " \
199 "source ${loadaddr}\0" \
200 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
201 "mmcboot=echo Booting from mmc ...; " \
203 "bootm ${loadaddr}\0" \
204 "loaduimage_ubi=ubi part ubi; " \
205 "ubifsmount ubi:root; " \
206 "ubifsload ${loadaddr} /boot/uImage\0" \
207 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
208 "nandboot=echo Booting from nand ...; " \
210 "run loaduimage_nand; " \
211 "bootm ${loadaddr}\0" \
212 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
213 "if run loadbootscript; then " \
216 "if run loaduimage; then " \
218 "else run nandboot; " \
221 "else run nandboot; fi\0"
223 #endif /* CONFIG_FLASHCARD */
225 /* Miscellaneous configurable options */
226 #define CONFIG_SYS_LONGHELP /* undef to save memory */
227 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
228 #define CONFIG_AUTO_COMPLETE
229 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
230 /* Print Buffer Size */
231 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
232 sizeof(CONFIG_SYS_PROMPT) + 16)
233 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
235 /* Boot Argument Buffer Size */
236 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
238 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
239 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
240 0x07000000) /* 112 MB */
242 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
245 * OMAP3 has 12 GP timers, they can be driven by the system clock
246 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
247 * This rate is divided by a local divisor.
249 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
250 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
252 /* Physical Memory Map */
253 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
254 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
255 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
257 /* NAND and environment organization */
258 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
260 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
261 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
262 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
263 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
264 CONFIG_SYS_INIT_RAM_SIZE - \
265 GENERATED_GBL_DATA_SIZE)
268 #define CONFIG_SYS_SRAM_START 0x40200000
269 #define CONFIG_SYS_SRAM_SIZE 0x10000
271 /* Defines for SPL */
272 #define CONFIG_SPL_FRAMEWORK
273 #define CONFIG_SPL_NAND_SIMPLE
275 #define CONFIG_SPL_NAND_BASE
276 #define CONFIG_SPL_NAND_DRIVERS
277 #define CONFIG_SPL_NAND_ECC
278 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
279 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
280 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
282 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
283 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
284 CONFIG_SPL_TEXT_BASE)
286 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
287 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
289 /* NAND boot config */
290 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
291 #define CONFIG_SYS_NAND_PAGE_COUNT 64
292 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
293 #define CONFIG_SYS_NAND_OOBSIZE 64
294 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
295 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
296 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
297 13, 14, 16, 17, 18, 19, 20, 21, 22, \
298 23, 24, 25, 26, 27, 28, 30, 31, 32, \
299 33, 34, 35, 36, 37, 38, 39, 40, 41, \
300 42, 44, 45, 46, 47, 48, 49, 50, 51, \
303 #define CONFIG_SYS_NAND_ECCSIZE 512
304 #define CONFIG_SYS_NAND_ECCBYTES 13
305 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
307 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
309 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
310 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
312 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
313 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
315 #define CONFIG_SYS_ALT_MEMTEST
316 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
317 #endif /* __CONFIG_H */