include/configs/tricorder.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * (C) Copyright 2012
   8  * Corscience GmbH & Co. KG
   9  * Thomas Weber <weber@corscience.de>
  10  *
  11  * Configuration settings for the Tricorder board.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 #define CONFIG_MACH_TYPE                MACH_TYPE_TRICORDER
  20 /*
  21  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  22  * 64 bytes before this address should be set aside for u-boot.img's
  23  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  24  * other needs.
  25  */
  26 #define CONFIG_SYS_TEXT_BASE            0x80100000
  27
  28 #include <asm/arch/cpu.h>               /* get chip and board defs */
  29 #include <asm/arch/omap.h>
  30
  31 /* Clock Defines */
  32 #define V_OSCK                          26000000 /* Clock output from T2 */
  33 #define V_SCLK                          (V_OSCK >> 1)
  34
  35 #define CONFIG_MISC_INIT_R
  36
  37 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  38 #define CONFIG_SETUP_MEMORY_TAGS
  39 #define CONFIG_INITRD_TAG
  40 #define CONFIG_REVISION_TAG
  41
  42 /* Size of malloc() pool */
  43 #define CONFIG_SYS_MALLOC_LEN           (1024*1024)
  44
  45 /* Hardware drivers */
  46
  47 /* NS16550 Configuration */
  48 #define CONFIG_SYS_NS16550_SERIAL
  49 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  50 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  51
  52 /* select serial console configuration */
  53 #define CONFIG_CONS_INDEX               3
  54 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  55 #define CONFIG_SERIAL3                  3
  56 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  57                                         115200}
  58
  59 /* I2C */
  60 #define CONFIG_SYS_I2C
  61 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
  62 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
  63
  64
  65 /* EEPROM */
  66 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
  67 #define CONFIG_SYS_EEPROM_BUS_NUM       1
  68
  69 /* TWL4030 */
  70 #define CONFIG_TWL4030_LED
  71
  72 /* Board NAND Info */
  73 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
  74
  75 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
  76                                                         /* to access nand */
  77 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  78                                                         /* to access nand at */
  79                                                         /* CS0 */
  80 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  81                                                         /* devices */
  82 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  83 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  84
  85 /* needed for ubi */
  86 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  87 #define CONFIG_MTD_PARTITIONS
  88
  89 /* Environment information (this is the common part) */
  90
  91
  92 /* hang() the board on panic() */
  93 #define CONFIG_PANIC_HANG
  94
  95 /* environment placement (for NAND), is different for FLASHCARD but does not
  96  * harm there */
  97 #define CONFIG_ENV_OFFSET               0x120000    /* env start */
  98 #define CONFIG_ENV_OFFSET_REDUND        0x2A0000    /* redundant env start */
  99 #define CONFIG_ENV_SIZE                 (16 << 10)  /* use 16KiB for env */
 100 #define CONFIG_ENV_RANGE                (384 << 10) /* allow badblocks in env */
 101
 102 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
 103  * value can not be used here! */
 104 #define CONFIG_LOADADDR         0x82000000
 105
 106 #define CONFIG_COMMON_ENV_SETTINGS \
 107         "console=ttyO2,115200n8\0" \
 108         "mmcdev=0\0" \
 109         "vram=3M\0" \
 110         "defaultdisplay=lcd\0" \
 111         "kernelopts=mtdoops.mtddev=3\0" \
 112         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
 113         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
 114         "commonargs=" \
 115                 "setenv bootargs console=${console} " \
 116                 "${mtdparts} " \
 117                 "${kernelopts} " \
 118                 "vt.global_cursor_default=0 " \
 119                 "vram=${vram} " \
 120                 "omapdss.def_disp=${defaultdisplay}\0"
 121
 122 #define CONFIG_BOOTCOMMAND "run autoboot"
 123
 124 /* specific environment settings for different use cases
 125  * FLASHCARD: used to run a rdimage from sdcard to program the device
 126  * 'NORMAL': used to boot kernel from sdcard, nand, ...
 127  *
 128  * The main aim for the FLASHCARD skin is to have an embedded environment
 129  * which will not be influenced by any data already on the device.
 130  */
 131 #ifdef CONFIG_FLASHCARD
 132 /* the rdaddr is 16 MiB before the loadaddr */
 133 #define CONFIG_ENV_RDADDR       "rdaddr=0x81000000\0"
 134
 135 #define CONFIG_EXTRA_ENV_SETTINGS \
 136         CONFIG_COMMON_ENV_SETTINGS \
 137         CONFIG_ENV_RDADDR \
 138         "autoboot=" \
 139         "run commonargs; " \
 140         "setenv bootargs ${bootargs} " \
 141                 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
 142                 "rdinit=/sbin/init; " \
 143         "mmc dev ${mmcdev}; mmc rescan; " \
 144         "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
 145         "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
 146         "bootm ${loadaddr} ${rdaddr}\0"
 147
 148 #else /* CONFIG_FLASHCARD */
 149
 150 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
 151
 152 #define CONFIG_EXTRA_ENV_SETTINGS \
 153         CONFIG_COMMON_ENV_SETTINGS \
 154         "mmcargs=" \
 155                 "run commonargs; " \
 156                 "setenv bootargs ${bootargs} " \
 157                 "root=/dev/mmcblk0p2 " \
 158                 "rootwait " \
 159                 "rw\0" \
 160         "nandargs=" \
 161                 "run commonargs; " \
 162                 "setenv bootargs ${bootargs} " \
 163                 "root=ubi0:root " \
 164                 "ubi.mtd=7 " \
 165                 "rootfstype=ubifs " \
 166                 "ro\0" \
 167         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 168         "bootscript=echo Running bootscript from mmc ...; " \
 169                 "source ${loadaddr}\0" \
 170         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 171         "mmcboot=echo Booting from mmc ...; " \
 172                 "run mmcargs; " \
 173                 "bootm ${loadaddr}\0" \
 174         "loaduimage_ubi=ubi part ubi; " \
 175                 "ubifsmount ubi:root; " \
 176                 "ubifsload ${loadaddr} /boot/uImage\0" \
 177         "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
 178         "nandboot=echo Booting from nand ...; " \
 179                 "run nandargs; " \
 180                 "run loaduimage_nand; " \
 181                 "bootm ${loadaddr}\0" \
 182         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 183                         "if run loadbootscript; then " \
 184                                 "run bootscript; " \
 185                         "else " \
 186                                 "if run loaduimage; then " \
 187                                         "run mmcboot; " \
 188                                 "else run nandboot; " \
 189                                 "fi; " \
 190                         "fi; " \
 191                 "else run nandboot; fi\0"
 192
 193 #endif /* CONFIG_FLASHCARD */
 194
 195 /* Miscellaneous configurable options */
 196 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 197 #define CONFIG_CMDLINE_EDITING          /* enable cmdline history */
 198 #define CONFIG_AUTO_COMPLETE
 199 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 200
 201 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x00000000)
 202 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 203                                         0x07000000) /* 112 MB */
 204
 205 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 206
 207 /*
 208  * OMAP3 has 12 GP timers, they can be driven by the system clock
 209  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 210  * This rate is divided by a local divisor.
 211  */
 212 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 213 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
 214
 215 /*  Physical Memory Map  */
 216 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
 217 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
 218 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
 219
 220 /* NAND and environment organization  */
 221 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 222
 223 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 224 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 225 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 226 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 227                                                 CONFIG_SYS_INIT_RAM_SIZE - \
 228                                                 GENERATED_GBL_DATA_SIZE)
 229
 230 /* SRAM config */
 231 #define CONFIG_SYS_SRAM_START           0x40200000
 232 #define CONFIG_SYS_SRAM_SIZE            0x10000
 233
 234 /* Defines for SPL */
 235 #define CONFIG_SPL_FRAMEWORK
 236
 237 #define CONFIG_SPL_NAND_BASE
 238 #define CONFIG_SPL_NAND_DRIVERS
 239 #define CONFIG_SPL_NAND_ECC
 240 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
 241 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 242
 243 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 244 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 245                                          CONFIG_SPL_TEXT_BASE)
 246
 247 #define CONFIG_SPL_BSS_START_ADDR       0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
 248 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 249
 250 /* NAND boot config */
 251 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 252 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 253 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 254 #define CONFIG_SYS_NAND_OOBSIZE         64
 255 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 256 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 257 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
 258                                          13, 14, 16, 17, 18, 19, 20, 21, 22, \
 259                                          23, 24, 25, 26, 27, 28, 30, 31, 32, \
 260                                          33, 34, 35, 36, 37, 38, 39, 40, 41, \
 261                                          42, 44, 45, 46, 47, 48, 49, 50, 51, \
 262                                          52, 53, 54, 55, 56}
 263
 264 #define CONFIG_SYS_NAND_ECCSIZE         512
 265 #define CONFIG_SYS_NAND_ECCBYTES        13
 266 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 267
 268 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 269
 270 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
 271 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x100000
 272
 273 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 274 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
 275
 276 #define CONFIG_SYS_ALT_MEMTEST
 277 #define CONFIG_SYS_MEMTEST_SCRATCH      0x81000000
 278 #endif /* __CONFIG_H */