include/configs/tricorder.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * (C) Copyright 2012
   8  * Corscience GmbH & Co. KG
   9  * Thomas Weber <weber@corscience.de>
  10  *
  11  * Configuration settings for the Tricorder board.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 #define CONFIG_MACH_TYPE                MACH_TYPE_TRICORDER
  20 /*
  21  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  22  * 64 bytes before this address should be set aside for u-boot.img's
  23  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  24  * other needs.
  25  */
  26 #define CONFIG_SYS_TEXT_BASE            0x80100000
  27
  28 #include <asm/arch/cpu.h>               /* get chip and board defs */
  29 #include <asm/arch/omap.h>
  30
  31 /* Clock Defines */
  32 #define V_OSCK                          26000000 /* Clock output from T2 */
  33 #define V_SCLK                          (V_OSCK >> 1)
  34
  35 #define CONFIG_MISC_INIT_R
  36
  37 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  38 #define CONFIG_SETUP_MEMORY_TAGS
  39 #define CONFIG_INITRD_TAG
  40 #define CONFIG_REVISION_TAG
  41
  42 /* Size of malloc() pool */
  43 #define CONFIG_SYS_MALLOC_LEN           (1024*1024)
  44
  45 /* Hardware drivers */
  46
  47 /* NS16550 Configuration */
  48 #define CONFIG_SYS_NS16550_SERIAL
  49 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  50 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  51
  52 /* select serial console configuration */
  53 #define CONFIG_CONS_INDEX               3
  54 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  55 #define CONFIG_SERIAL3                  3
  56 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  57                                         115200}
  58
  59 /* I2C */
  60 #define CONFIG_SYS_I2C
  61
  62
  63 /* EEPROM */
  64 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
  65 #define CONFIG_SYS_EEPROM_BUS_NUM       1
  66
  67 /* TWL4030 */
  68 #define CONFIG_TWL4030_LED
  69
  70 /* Board NAND Info */
  71 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
  72
  73 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
  74                                                         /* to access nand */
  75 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  76                                                         /* to access nand at */
  77                                                         /* CS0 */
  78 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
  79                                                         /* devices */
  80 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  81 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
  82
  83 /* needed for ubi */
  84 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  85 #define CONFIG_MTD_PARTITIONS
  86
  87 /* Environment information (this is the common part) */
  88
  89
  90 /* hang() the board on panic() */
  91
  92 /* environment placement (for NAND), is different for FLASHCARD but does not
  93  * harm there */
  94 #define CONFIG_ENV_OFFSET               0x120000    /* env start */
  95 #define CONFIG_ENV_OFFSET_REDUND        0x2A0000    /* redundant env start */
  96 #define CONFIG_ENV_SIZE                 (16 << 10)  /* use 16KiB for env */
  97 #define CONFIG_ENV_RANGE                (384 << 10) /* allow badblocks in env */
  98
  99 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
 100  * value can not be used here! */
 101 #define CONFIG_LOADADDR         0x82000000
 102
 103 #define CONFIG_COMMON_ENV_SETTINGS \
 104         "console=ttyO2,115200n8\0" \
 105         "mmcdev=0\0" \
 106         "vram=3M\0" \
 107         "defaultdisplay=lcd\0" \
 108         "kernelopts=mtdoops.mtddev=3\0" \
 109         "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
 110         "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
 111         "commonargs=" \
 112                 "setenv bootargs console=${console} " \
 113                 "${mtdparts} " \
 114                 "${kernelopts} " \
 115                 "vt.global_cursor_default=0 " \
 116                 "vram=${vram} " \
 117                 "omapdss.def_disp=${defaultdisplay}\0"
 118
 119 #define CONFIG_BOOTCOMMAND "run autoboot"
 120
 121 /* specific environment settings for different use cases
 122  * FLASHCARD: used to run a rdimage from sdcard to program the device
 123  * 'NORMAL': used to boot kernel from sdcard, nand, ...
 124  *
 125  * The main aim for the FLASHCARD skin is to have an embedded environment
 126  * which will not be influenced by any data already on the device.
 127  */
 128 #ifdef CONFIG_FLASHCARD
 129 /* the rdaddr is 16 MiB before the loadaddr */
 130 #define CONFIG_ENV_RDADDR       "rdaddr=0x81000000\0"
 131
 132 #define CONFIG_EXTRA_ENV_SETTINGS \
 133         CONFIG_COMMON_ENV_SETTINGS \
 134         CONFIG_ENV_RDADDR \
 135         "autoboot=" \
 136         "run commonargs; " \
 137         "setenv bootargs ${bootargs} " \
 138                 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
 139                 "rdinit=/sbin/init; " \
 140         "mmc dev ${mmcdev}; mmc rescan; " \
 141         "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
 142         "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
 143         "bootm ${loadaddr} ${rdaddr}\0"
 144
 145 #else /* CONFIG_FLASHCARD */
 146
 147 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
 148
 149 #define CONFIG_EXTRA_ENV_SETTINGS \
 150         CONFIG_COMMON_ENV_SETTINGS \
 151         "mmcargs=" \
 152                 "run commonargs; " \
 153                 "setenv bootargs ${bootargs} " \
 154                 "root=/dev/mmcblk0p2 " \
 155                 "rootwait " \
 156                 "rw\0" \
 157         "nandargs=" \
 158                 "run commonargs; " \
 159                 "setenv bootargs ${bootargs} " \
 160                 "root=ubi0:root " \
 161                 "ubi.mtd=7 " \
 162                 "rootfstype=ubifs " \
 163                 "ro\0" \
 164         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 165         "bootscript=echo Running bootscript from mmc ...; " \
 166                 "source ${loadaddr}\0" \
 167         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 168         "mmcboot=echo Booting from mmc ...; " \
 169                 "run mmcargs; " \
 170                 "bootm ${loadaddr}\0" \
 171         "loaduimage_ubi=ubi part ubi; " \
 172                 "ubifsmount ubi:root; " \
 173                 "ubifsload ${loadaddr} /boot/uImage\0" \
 174         "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
 175         "nandboot=echo Booting from nand ...; " \
 176                 "run nandargs; " \
 177                 "run loaduimage_nand; " \
 178                 "bootm ${loadaddr}\0" \
 179         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 180                         "if run loadbootscript; then " \
 181                                 "run bootscript; " \
 182                         "else " \
 183                                 "if run loaduimage; then " \
 184                                         "run mmcboot; " \
 185                                 "else run nandboot; " \
 186                                 "fi; " \
 187                         "fi; " \
 188                 "else run nandboot; fi\0"
 189
 190 #endif /* CONFIG_FLASHCARD */
 191
 192 /* Miscellaneous configurable options */
 193 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 194 #define CONFIG_CMDLINE_EDITING          /* enable cmdline history */
 195 #define CONFIG_AUTO_COMPLETE
 196 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 197
 198 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x00000000)
 199 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 200                                         0x07000000) /* 112 MB */
 201
 202 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 203
 204 /*
 205  * OMAP3 has 12 GP timers, they can be driven by the system clock
 206  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 207  * This rate is divided by a local divisor.
 208  */
 209 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 210 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
 211
 212 /*  Physical Memory Map  */
 213 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
 214 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
 215 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
 216
 217 /* NAND and environment organization  */
 218 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 219
 220 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 221 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 222 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 223 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 224                                                 CONFIG_SYS_INIT_RAM_SIZE - \
 225                                                 GENERATED_GBL_DATA_SIZE)
 226
 227 /* SRAM config */
 228 #define CONFIG_SYS_SRAM_START           0x40200000
 229 #define CONFIG_SYS_SRAM_SIZE            0x10000
 230
 231 /* Defines for SPL */
 232 #define CONFIG_SPL_FRAMEWORK
 233
 234 #define CONFIG_SPL_NAND_BASE
 235 #define CONFIG_SPL_NAND_DRIVERS
 236 #define CONFIG_SPL_NAND_ECC
 237 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
 238 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 239
 240 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 241 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 242                                          CONFIG_SPL_TEXT_BASE)
 243
 244 #define CONFIG_SPL_BSS_START_ADDR       0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
 245 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 246
 247 /* NAND boot config */
 248 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 249 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 250 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 251 #define CONFIG_SYS_NAND_OOBSIZE         64
 252 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 253 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 254 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
 255                                          13, 14, 16, 17, 18, 19, 20, 21, 22, \
 256                                          23, 24, 25, 26, 27, 28, 30, 31, 32, \
 257                                          33, 34, 35, 36, 37, 38, 39, 40, 41, \
 258                                          42, 44, 45, 46, 47, 48, 49, 50, 51, \
 259                                          52, 53, 54, 55, 56}
 260
 261 #define CONFIG_SYS_NAND_ECCSIZE         512
 262 #define CONFIG_SYS_NAND_ECCBYTES        13
 263 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 264
 265 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 266
 267 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
 268 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x100000
 269
 270 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 271 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
 272
 273 #define CONFIG_SYS_ALT_MEMTEST
 274 #define CONFIG_SYS_MEMTEST_SCRATCH      0x81000000
 275 #endif /* __CONFIG_H */