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1 /*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 *
7 * (C) Copyright 2012
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
10 *
11 * Configuration settings for the Tricorder board.
12 *
13 * SPDX-License-Identifier: GPL-2.0+
14 */
15
16 #ifndef __CONFIG_H
17 #define __CONFIG_H
18
19 #define CONFIG_SYS_CACHELINE_SIZE 64
20
21 /* High Level Configuration Options */
22 #define CONFIG_SYS_THUMB_BUILD
23 #define CONFIG_OMAP /* in a TI OMAP core */
24 #define CONFIG_OMAP_COMMON
25 /* Common ARM Erratas */
26 #define CONFIG_ARM_ERRATA_454179
27 #define CONFIG_ARM_ERRATA_430973
28 #define CONFIG_ARM_ERRATA_621766
29
30 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
31 /*
32 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
33 * 64 bytes before this address should be set aside for u-boot.img's
34 * header. That is 0x800FFFC0--0x80100000 should not be used for any
35 * other needs.
36 */
37 #define CONFIG_SYS_TEXT_BASE 0x80100000
38
39 #define CONFIG_SDRC /* The chip has SDRC controller */
40
41 #include <asm/arch/cpu.h> /* get chip and board defs */
42 #include <asm/arch/omap.h>
43
44 /* Display CPU and Board information */
45 #define CONFIG_DISPLAY_CPUINFO
46 #define CONFIG_DISPLAY_BOARDINFO
47
48 #define CONFIG_SILENT_CONSOLE
49 #define CONFIG_ZERO_BOOTDELAY_CHECK
50
51 /* Clock Defines */
52 #define V_OSCK 26000000 /* Clock output from T2 */
53 #define V_SCLK (V_OSCK >> 1)
54
55 #define CONFIG_MISC_INIT_R
56
57 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
58 #define CONFIG_SETUP_MEMORY_TAGS
59 #define CONFIG_INITRD_TAG
60 #define CONFIG_REVISION_TAG
61
62 /* Size of malloc() pool */
63 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
64
65 /* Hardware drivers */
66
67 /* GPIO support */
68 #define CONFIG_OMAP_GPIO
69
70 /* GPIO banks */
71 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */
72
73 /* LED support */
74 #define CONFIG_STATUS_LED
75 #define CONFIG_BOARD_SPECIFIC_LED
76 #define CONFIG_CMD_LED /* LED command */
77 #define STATUS_LED_BIT (1 << 0)
78 #define STATUS_LED_STATE STATUS_LED_ON
79 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
80 #define STATUS_LED_BIT1 (1 << 1)
81 #define STATUS_LED_STATE1 STATUS_LED_ON
82 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
83 #define STATUS_LED_BIT2 (1 << 2)
84 #define STATUS_LED_STATE2 STATUS_LED_ON
85 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
86
87 /* NS16550 Configuration */
88 #define CONFIG_SYS_NS16550_SERIAL
89 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
90 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
91
92 /* select serial console configuration */
93 #define CONFIG_CONS_INDEX 3
94 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
95 #define CONFIG_SERIAL3 3
96 #define CONFIG_BAUDRATE 115200
97 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
98 115200}
99
100 /* MMC */
101 #define CONFIG_GENERIC_MMC
102 #define CONFIG_MMC
103 #define CONFIG_OMAP_HSMMC
104 #define CONFIG_DOS_PARTITION
105
106 /* I2C */
107 #define CONFIG_SYS_I2C
108 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
109 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
110 #define CONFIG_SYS_I2C_OMAP34XX
111
112
113 /* EEPROM */
114 #define CONFIG_CMD_EEPROM
115 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
116 #define CONFIG_SYS_EEPROM_BUS_NUM 1
117
118 /* TWL4030 */
119 #define CONFIG_TWL4030_POWER
120 #define CONFIG_TWL4030_LED
121
122 /* Board NAND Info */
123 #define CONFIG_SYS_NO_FLASH /* no NOR flash */
124 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
125 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
126 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
127 "128k(SPL)," \
128 "1m(u-boot)," \
129 "384k(u-boot-env1)," \
130 "1152k(mtdoops)," \
131 "384k(u-boot-env2)," \
132 "5m(kernel)," \
133 "2m(fdt)," \
134 "-(ubi)"
135
136 #define CONFIG_NAND_OMAP_GPMC
137 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
138 /* to access nand */
139 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
140 /* to access nand at */
141 /* CS0 */
142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
143 /* devices */
144 #define CONFIG_BCH
145 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
146 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
147
148 /* commands to include */
149 #define CONFIG_CMD_EXT2 /* EXT2 Support */
150 #define CONFIG_CMD_FAT /* FAT support */
151 #define CONFIG_CMD_MMC /* MMC support */
152 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
153 #define CONFIG_CMD_NAND /* NAND support */
154 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
155 #define CONFIG_CMD_UBI /* UBI commands */
156 #define CONFIG_CMD_UBIFS /* UBIFS commands */
157 #define CONFIG_LZO /* LZO is needed for UBIFS */
158
159 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
160
161 /* needed for ubi */
162 #define CONFIG_RBTREE
163 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
164 #define CONFIG_MTD_PARTITIONS
165
166 /* Environment information (this is the common part) */
167
168 #define CONFIG_BOOTDELAY 0
169
170 /* hang() the board on panic() */
171 #define CONFIG_PANIC_HANG
172
173 /* environment placement (for NAND), is different for FLASHCARD but does not
174 * harm there */
175 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
176 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
177 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
178 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
179
180 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
181 * value can not be used here! */
182 #define CONFIG_LOADADDR 0x82000000
183
184 #define CONFIG_COMMON_ENV_SETTINGS \
185 "console=ttyO2,115200n8\0" \
186 "mmcdev=0\0" \
187 "vram=3M\0" \
188 "defaultdisplay=lcd\0" \
189 "kernelopts=mtdoops.mtddev=3\0" \
190 "mtdparts=" MTDPARTS_DEFAULT "\0" \
191 "mtdids=" MTDIDS_DEFAULT "\0" \
192 "commonargs=" \
193 "setenv bootargs console=${console} " \
194 "${mtdparts} " \
195 "${kernelopts} " \
196 "vt.global_cursor_default=0 " \
197 "vram=${vram} " \
198 "omapdss.def_disp=${defaultdisplay}\0"
199
200 #define CONFIG_BOOTCOMMAND "run autoboot"
201
202 /* specific environment settings for different use cases
203 * FLASHCARD: used to run a rdimage from sdcard to program the device
204 * 'NORMAL': used to boot kernel from sdcard, nand, ...
205 *
206 * The main aim for the FLASHCARD skin is to have an embedded environment
207 * which will not be influenced by any data already on the device.
208 */
209 #ifdef CONFIG_FLASHCARD
210
211 #define CONFIG_ENV_IS_NOWHERE
212
213 /* the rdaddr is 16 MiB before the loadaddr */
214 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
215
216 #define CONFIG_EXTRA_ENV_SETTINGS \
217 CONFIG_COMMON_ENV_SETTINGS \
218 CONFIG_ENV_RDADDR \
219 "autoboot=" \
220 "run commonargs; " \
221 "setenv bootargs ${bootargs} " \
222 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
223 "rdinit=/sbin/init; " \
224 "mmc dev ${mmcdev}; mmc rescan; " \
225 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
226 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
227 "bootm ${loadaddr} ${rdaddr}\0"
228
229 #else /* CONFIG_FLASHCARD */
230
231 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
232
233 #define CONFIG_ENV_IS_IN_NAND
234
235 #define CONFIG_EXTRA_ENV_SETTINGS \
236 CONFIG_COMMON_ENV_SETTINGS \
237 "mmcargs=" \
238 "run commonargs; " \
239 "setenv bootargs ${bootargs} " \
240 "root=/dev/mmcblk0p2 " \
241 "rootwait " \
242 "rw\0" \
243 "nandargs=" \
244 "run commonargs; " \
245 "setenv bootargs ${bootargs} " \
246 "root=ubi0:root " \
247 "ubi.mtd=7 " \
248 "rootfstype=ubifs " \
249 "ro\0" \
250 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
251 "bootscript=echo Running bootscript from mmc ...; " \
252 "source ${loadaddr}\0" \
253 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
254 "mmcboot=echo Booting from mmc ...; " \
255 "run mmcargs; " \
256 "bootm ${loadaddr}\0" \
257 "loaduimage_ubi=ubi part ubi; " \
258 "ubifsmount ubi:root; " \
259 "ubifsload ${loadaddr} /boot/uImage\0" \
260 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
261 "nandboot=echo Booting from nand ...; " \
262 "run nandargs; " \
263 "run loaduimage_nand; " \
264 "bootm ${loadaddr}\0" \
265 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
266 "if run loadbootscript; then " \
267 "run bootscript; " \
268 "else " \
269 "if run loaduimage; then " \
270 "run mmcboot; " \
271 "else run nandboot; " \
272 "fi; " \
273 "fi; " \
274 "else run nandboot; fi\0"
275
276 #endif /* CONFIG_FLASHCARD */
277
278 /* Miscellaneous configurable options */
279 #define CONFIG_SYS_LONGHELP /* undef to save memory */
280 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
281 #define CONFIG_AUTO_COMPLETE
282 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
283 /* Print Buffer Size */
284 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
285 sizeof(CONFIG_SYS_PROMPT) + 16)
286 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
287
288 /* Boot Argument Buffer Size */
289 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
290
291 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
292 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
293 0x07000000) /* 112 MB */
294
295 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
296
297 /*
298 * OMAP3 has 12 GP timers, they can be driven by the system clock
299 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
300 * This rate is divided by a local divisor.
301 */
302 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
303 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
304
305 /* Physical Memory Map */
306 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
307 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
308 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
309
310 /* NAND and environment organization */
311 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
312
313 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
314 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
315 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
316 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
317 CONFIG_SYS_INIT_RAM_SIZE - \
318 GENERATED_GBL_DATA_SIZE)
319
320 /* SRAM config */
321 #define CONFIG_SYS_SRAM_START 0x40200000
322 #define CONFIG_SYS_SRAM_SIZE 0x10000
323
324 /* Defines for SPL */
325 #define CONFIG_SPL_FRAMEWORK
326 #define CONFIG_SPL_NAND_SIMPLE
327
328 #define CONFIG_SPL_BOARD_INIT
329 #define CONFIG_SPL_GPIO_SUPPORT
330 #define CONFIG_SPL_LIBCOMMON_SUPPORT
331 #define CONFIG_SPL_LIBDISK_SUPPORT
332 #define CONFIG_SPL_I2C_SUPPORT
333 #define CONFIG_SPL_LIBGENERIC_SUPPORT
334 #define CONFIG_SPL_SERIAL_SUPPORT
335 #define CONFIG_SPL_POWER_SUPPORT
336 #define CONFIG_SPL_NAND_SUPPORT
337 #define CONFIG_SPL_NAND_BASE
338 #define CONFIG_SPL_NAND_DRIVERS
339 #define CONFIG_SPL_NAND_ECC
340 #define CONFIG_SPL_MMC_SUPPORT
341 #define CONFIG_SPL_FAT_SUPPORT
342 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
343 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
344 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
345 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
346
347 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
348 #define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */
349
350 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
351 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
352
353 /* NAND boot config */
354 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
355 #define CONFIG_SYS_NAND_PAGE_COUNT 64
356 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
357 #define CONFIG_SYS_NAND_OOBSIZE 64
358 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
359 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
360 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
361 13, 14, 16, 17, 18, 19, 20, 21, 22, \
362 23, 24, 25, 26, 27, 28, 30, 31, 32, \
363 33, 34, 35, 36, 37, 38, 39, 40, 41, \
364 42, 44, 45, 46, 47, 48, 49, 50, 51, \
365 52, 53, 54, 55, 56}
366
367 #define CONFIG_SYS_NAND_ECCSIZE 512
368 #define CONFIG_SYS_NAND_ECCBYTES 13
369 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
370
371 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
372
373 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
374 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
375
376 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
377 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
378
379 #define CONFIG_SYS_ALT_MEMTEST
380 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
381 #endif /* __CONFIG_H */