]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/trizepsiv.h
Merge branch 'master' of git://git.denx.de/u-boot
[people/ms/u-boot.git] / include / configs / trizepsiv.h
1 /*
2 * (C) Copyright 2007
3 * Stefano Babic, DENX Gmbh, sbabic@denx.de
4 *
5 * (C) Copyright 2004
6 * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
7 *
8 * (C) Copyright 2002
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 *
11 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
14 *
15 * Configuation settings for the LUBBOCK board.
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36 #ifndef __CONFIG_H
37 #define __CONFIG_H
38
39 /*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43 #define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
44
45 #define CONFIG_MMC 1
46 #define BOARD_LATE_INIT 1
47
48 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
49
50 #define RTC
51
52 /*
53 * Size of malloc() pool
54 */
55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
56 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
57
58 /*
59 * Hardware drivers
60 */
61
62 /*
63 * select serial console configuration
64 */
65 #define CONFIG_SERIAL_MULTI
66 #define CONFIG_FFUART 1 /* we use FFUART on Conxs */
67 #define CONFIG_BTUART 1 /* we use BTUART on Conxs */
68 #define CONFIG_STUART 1 /* we use STUART on Conxs */
69
70 /* allow to overwrite serial and ethaddr */
71 #define CONFIG_ENV_OVERWRITE
72
73 #define CONFIG_BAUDRATE 38400
74
75 #define CONFIG_DOS_PARTITION 1
76
77 /*
78 * Command line configuration.
79 */
80 #include <config_cmd_default.h>
81
82 #define CONFIG_CMD_FAT
83 #define CONFIG_CMD_IMLS
84 #define CONFIG_CMD_PING
85 #define CONFIG_CMD_USB
86
87 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
88
89 #undef CONFIG_SHOW_BOOT_PROGRESS
90
91 #define CONFIG_BOOTDELAY 3
92 #define CONFIG_SERVERIP 192.168.1.99
93 #define CONFIG_BOOTCOMMAND "run boot_flash"
94 #define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
95 " rw root=/dev/ram initrd=0xa0800000,5m"
96
97 #define CONFIG_EXTRA_ENV_SETTINGS \
98 "program_boot_mmc=" \
99 "mw.b 0xa0010000 0xff 0x20000; " \
100 "if mmcinit && " \
101 "fatload mmc 0 0xa0010000 u-boot.bin; " \
102 "then " \
103 "protect off 0x0 0x1ffff; " \
104 "erase 0x0 0x1ffff; " \
105 "cp.b 0xa0010000 0x0 0x20000; " \
106 "fi\0" \
107 "program_uzImage_mmc=" \
108 "mw.b 0xa0010000 0xff 0x180000; " \
109 "if mmcinit && " \
110 "fatload mmc 0 0xa0010000 uzImage; " \
111 "then " \
112 "protect off 0x40000 0x1bffff; " \
113 "erase 0x40000 0x1bffff; " \
114 "cp.b 0xa0010000 0x40000 0x180000; " \
115 "fi\0" \
116 "program_ramdisk_mmc=" \
117 "mw.b 0xa0010000 0xff 0x500000; " \
118 "if mmcinit && " \
119 "fatload mmc 0 0xa0010000 ramdisk.gz; " \
120 "then " \
121 "protect off 0x1c0000 0x6bffff; " \
122 "erase 0x1c0000 0x6bffff; " \
123 "cp.b 0xa0010000 0x1c0000 0x500000; " \
124 "fi\0" \
125 "boot_mmc=" \
126 "if mmcinit && " \
127 "fatload mmc 0 0xa0030000 uzImage && " \
128 "fatload mmc 0 0xa0800000 ramdisk.gz; " \
129 "then " \
130 "bootm 0xa0030000; " \
131 "fi\0" \
132 "boot_flash=" \
133 "cp.b 0x1c0000 0xa0800000 0x500000; " \
134 "bootm 0x40000\0" \
135
136 #define CONFIG_SETUP_MEMORY_TAGS 1
137 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
138 /* #define CONFIG_INITRD_TAG 1 */
139
140 #if defined(CONFIG_CMD_KGDB)
141 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
142 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
143 #endif
144
145 /*
146 * Miscellaneous configurable options
147 */
148 #define CONFIG_SYS_HUSH_PARSER 1
149 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
150
151 #define CONFIG_SYS_LONGHELP /* undef to save memory */
152 #ifdef CONFIG_SYS_HUSH_PARSER
153 #define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
154 #else
155 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
156 #endif
157 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
158 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
159 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
160 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
161 #define CONFIG_SYS_DEVICE_NULLDEV 1
162
163 #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
164 #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
165
166 #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
167
168 #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
169
170 #define CONFIG_SYS_HZ 1000
171 #define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
172
173 /* valid baudrates */
174 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
175
176 #ifdef CONFIG_MMC
177 #define CONFIG_PXA_MMC
178 #define CONFIG_CMD_MMC
179 #define CONFIG_SYS_MMC_BASE 0xF0000000
180 #endif
181
182 /*
183 * Stack sizes
184 *
185 * The stack sizes are set up in start.S using the settings below
186 */
187 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
188 #ifdef CONFIG_USE_IRQ
189 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
190 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
191 #endif
192
193 /*
194 * Physical Memory Map
195 */
196 #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
197 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
198 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
199 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
200 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
201 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
202 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
203 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
204 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
205
206 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
207
208 #define CONFIG_SYS_DRAM_BASE 0xa0000000
209 #define CONFIG_SYS_DRAM_SIZE 0x04000000
210
211 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
212
213 /*
214 * GPIO settings
215 */
216 #define CONFIG_SYS_GPSR0_VAL 0x00018000
217 #define CONFIG_SYS_GPSR1_VAL 0x00000000
218 #define CONFIG_SYS_GPSR2_VAL 0x400dc000
219 #define CONFIG_SYS_GPSR3_VAL 0x00000000
220 #define CONFIG_SYS_GPCR0_VAL 0x00000000
221 #define CONFIG_SYS_GPCR1_VAL 0x00000000
222 #define CONFIG_SYS_GPCR2_VAL 0x00000000
223 #define CONFIG_SYS_GPCR3_VAL 0x00000000
224 #define CONFIG_SYS_GPDR0_VAL 0x00018000
225 #define CONFIG_SYS_GPDR1_VAL 0x00028801
226 #define CONFIG_SYS_GPDR2_VAL 0x520dc000
227 #define CONFIG_SYS_GPDR3_VAL 0x0001E000
228 #define CONFIG_SYS_GAFR0_L_VAL 0x801c0000
229 #define CONFIG_SYS_GAFR0_U_VAL 0x00000013
230 #define CONFIG_SYS_GAFR1_L_VAL 0x6990100A
231 #define CONFIG_SYS_GAFR1_U_VAL 0x00000008
232 #define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
233 #define CONFIG_SYS_GAFR2_U_VAL 0x010900F2
234 #define CONFIG_SYS_GAFR3_L_VAL 0x54000003
235 #define CONFIG_SYS_GAFR3_U_VAL 0x00002401
236 #define CONFIG_SYS_GRER0_VAL 0x00000000
237 #define CONFIG_SYS_GRER1_VAL 0x00000000
238 #define CONFIG_SYS_GRER2_VAL 0x00000000
239 #define CONFIG_SYS_GRER3_VAL 0x00000000
240 #define CONFIG_SYS_GFER0_VAL 0x00000000
241 #define CONFIG_SYS_GFER1_VAL 0x00000000
242 #define CONFIG_SYS_GFER2_VAL 0x00000000
243 #define CONFIG_SYS_GFER3_VAL 0x00000020
244
245
246 #define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
247
248 /*
249 * Clock settings
250 */
251 #define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */
252 #define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
253
254 /*
255 * Memory settings
256 */
257
258 #define CONFIG_SYS_MSC0_VAL 0x4df84df0
259 #define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
260 #define CONFIG_SYS_MSC2_VAL 0xa26936d4
261 #define CONFIG_SYS_MDCNFG_VAL 0x880009C9
262 #define CONFIG_SYS_MDREFR_VAL 0x20ca201e
263 #define CONFIG_SYS_MDMRS_VAL 0x00220022
264
265 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000
266 #define CONFIG_SYS_SXCNFG_VAL 0x40044004
267
268 /*
269 * PCMCIA and CF Interfaces
270 */
271 #define CONFIG_SYS_MECR_VAL 0x00000001
272 #define CONFIG_SYS_MCMEM0_VAL 0x00004204
273 #define CONFIG_SYS_MCMEM1_VAL 0x00010204
274 #define CONFIG_SYS_MCATT0_VAL 0x00010504
275 #define CONFIG_SYS_MCATT1_VAL 0x00010504
276 #define CONFIG_SYS_MCIO0_VAL 0x00008407
277 #define CONFIG_SYS_MCIO1_VAL 0x0000c108
278
279 #define CONFIG_DRIVER_DM9000 1
280 #define CONFIG_DM9000_BASE 0x08000000
281 #define DM9000_IO CONFIG_DM9000_BASE
282 #define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
283
284 #define CONFIG_USB_OHCI_NEW 1
285 #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
286 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
287 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
288 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv"
289 #define CONFIG_USB_STORAGE 1
290 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
291
292 /*
293 * FLASH and environment organization
294 */
295
296 #define CONFIG_SYS_FLASH_CFI
297 #define CONFIG_FLASH_CFI_DRIVER 1
298
299 #define CONFIG_SYS_MONITOR_BASE 0
300 #define CONFIG_SYS_MONITOR_LEN 0x40000
301
302 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
303 #define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
304
305 /* timeout values are in ticks */
306 #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
307 #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
308
309 /* write flash less slowly */
310 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
311
312 /* Flash environment locations */
313 #define CONFIG_ENV_IS_IN_FLASH 1
314 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
315 #define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */
316 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
317
318 /* Address and size of Redundant Environment Sector */
319 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
320 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
321
322 #endif /* __CONFIG_H */